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Constraint generation for routing analog circuits
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 27th ACM/IEEE Design Automation Conference table of contents
Orlando, Florida, United States
Pages: 561 - 566  
Year of Publication: 1991
ISBN:0-89791-363-9
Authors
Umakanta Choudhury  Department of Electrical Engineering and Computer Sciences, UC Berkeley, CA
A. Sangiovanni-Vincentelli  Department of Electrical Engineering and Computer Sciences, UC Berkeley, CA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 7,   Downloads (12 Months): 19,   Citation Count: 14
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ABSTRACT

An approach for generating constraints on interconnect parasitics to drive the routing of analog circuits is presented. The approach involves (a) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the router while meeting the performance constraints, and (b) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information in differential circuits. A prototype constraint generator is described. It is hoped that the constraint-based approach suggested in this paper, if applied to both placement and routing, will reduce the need of time consuming layout-extraction-simulation iterations in the physical design phase of analog circuits.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
C.D. Kimble et al.,"Autorouted Analog VLSI," Proc. IEEE Custom Integrated Circuits Conference, 1985, pp. 72-78.
 
2
D. Garrod, R.A. Rutenbar and L.R. C'arley, "Automatic Layout of Custom Integrated Circuits in ANAGRAM," Proc. IEEE 1CCAD, Nov. 1988, pp. 544-547.
 
3
R.S. Gyurcsik and J.-C. /een, "A Generalized Approach to Routing Mixed Analog and Digital Signal Nets in a Channel," IEEE Journal of Solid-State Circuits, Vo124, No. 2, Apr. 1989, pp. 436-442.
 
4
U. Choudlaury and A. Sangiovatmi-Vincentelli, "Use of Performance Sensitivities in Rouling of Analog Circuits," To apper in Proc. International Symposium in Circuits and Systems, May 1990.
 
5
U. Choudhury, "Sensitivity Computation in SPICE3," Masters Thesis, U.C. Berkeley, Dec; 1988.
 
6
"The Switched Capacitor Network Simulator SWAP Reference Manual,", Silvar-Lisco, Release 2.0, Nov. 1983.
 
7
S.W. Director and R.A. Rohrer, "The Generalized Adjoint Network Sensitivities," IEEE Trans. Circuit Theor'y, Vol CT-16, Aug 1969, pp. 318-.323.
 
8
H. Yaghutiel, A. Sangiovanni-Vincentelli, and P.R. Gray, "A Methodology for Automated Layout of Switched-Capacitor Filters," Proc. IEEE ICCAD, pp. 444-447, 1986
 
9
H.Y. Koh, C.H. Sequin, and ER. Gray, "Automatic Layout Generation for CMOS Operational Amplifiers" Proc. IEEE ICCAD, 1988, pp. 548-551.
 
10
E. Malavasi, M. Chilanti and R. Guerrieri, "A General Router for Analog Layout" Proc. of Compeuro, 1989, pp. 549-551.
 
11
J. L. Bums and A. R. Newton, "SPARCS: A new Constraint-Based IC Symbolic Layout Spacer," Proc. IEEE Custom Integrated Circuits Conference, May 1986, pp. 534-539

CITED BY  14

Collaborative Colleagues:
Umakanta Choudhury: colleagues
A. Sangiovanni-Vincentelli: colleagues