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Architecture synthesis of high-performance application-specific processors
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 27th ACM/IEEE Design Automation Conference table of contents
Orlando, Florida, United States
Pages: 542 - 548  
Year of Publication: 1991
ISBN:0-89791-363-9
Authors
Mauricio Breternitz, Jr.  SRC-CMU CAD Center, ECE Dept, Carnegie Mellon University, Pittsburgh, PA
John Paul Shen  SRC-CMU CAD Center, ECE Dept, Carnegie Mellon University, Pittsburgh, PA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 6,   Downloads (12 Months): 14,   Citation Count: 12
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ABSTRACT

The key principles of the Application-Specific Processor Design (ASPD) methodology include: a semi-custom compilation-driven design/implementation approach, the exploitation of fine-grained parallelism for high performance, and the adaptation of datapath topology to the data transfers required by the application. The powerful microcode compilation techniques of Percolation Scheduling and Pipeline Scheduling extract and enhance the parallelism in the application object code to generate an optimized specification of the target processor. Implementation optimization is performed to allocate functional units and register files. Graph-coloring algorithms minimize the amount of hardware needed to exploit available parallelism. Data memory employs an organization with multiple banks. Compilation techniques are used to allocate data over the memory banks to enhance parallel access.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Z.J.Cendes and D.N.Shenton, "Adaptive Mesh Refinement in the Finite Element Computation of Magnetic Fields", IEEE Trans. Mag., 1985.
 
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P.G. Paulin and J. P. Knight, "'Force-Directed Scheduling for the Behavioral Synthesis of ASIC's", IEEE Trans. CAD, June 1989.
 
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Y.Neuvo, D.Chengyu and S.K.Mitra., " Interpolated Finite Impulse Response Filters", IEEE Trans. ASSP, June 1984,
 
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B.S. Haroun and M. I. Elmasry, "Automatic Synthesis of a Multi-Bus Architecture for DSP", ICCAD, Nov 1988.
 
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M. Breternitz Jr and J. P. Shen, "'Architecture Synthesis of High-Performance Application-Specific Processors", CMUCAD 90- 7, Mar 1990.

CITED BY  12

Collaborative Colleagues:
Mauricio Breternitz, Jr.: colleagues
John Paul Shen: colleagues