| Architecture synthesis of high-performance application-specific processors |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 27th ACM/IEEE Design Automation Conference
table of contents
Orlando, Florida, United States
Pages: 542 - 548
Year of Publication: 1991
ISBN:0-89791-363-9
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Downloads (6 Weeks): 1, Downloads (12 Months): 11, Citation Count: 12
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ABSTRACT
The key principles of the Application-Specific Processor Design (ASPD) methodology include: a semi-custom compilation-driven design/implementation approach, the exploitation of fine-grained parallelism for high performance, and the adaptation of datapath topology to the data transfers required by the application. The powerful microcode compilation techniques of Percolation Scheduling and Pipeline Scheduling extract and enhance the parallelism in the application object code to generate an optimized specification of the target processor. Implementation optimization is performed to allocate functional units and register files. Graph-coloring algorithms minimize the amount of hardware needed to exploit available parallelism. Data memory employs an organization with multiple banks. Compilation techniques are used to allocate data over the memory banks to enhance parallel access.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Michael C. McFarland , Alice C. Parker , Raul Camposano, Tutorial on high-level synthesis, Proceedings of the 25th ACM/IEEE conference on Design automation, p.330-336, June 12-15, 1988, Atlantic City, New Jersey, United States
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A. Wolfe , M. Breternitz, Jr. , C. Stephens , A. L. Ting , D. B. Kirk , R. P. Bianchini, Jr. , J. P. Shen, The white dwarf: a high-performance application-specific processor, Proceedings of the 15th Annual International Symposium on Computer architecture, p.212-222, May 30-June 02, 1988, Honolulu, Hawaii, United States
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P.G. Paulin and J. P. Knight, "'Force-Directed Scheduling for the Behavioral Synthesis of ASIC's", IEEE Trans. CAD, June 1989.
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M. Breternitz, Jr. , J. P. Shen, Organization of array data for concurrent memory access, Proceedings of the 21st annual workshop on Microprogramming and microarchitecture, p.97-99, November 28-December 02, 1988, San Diego, California, United States
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Y.Neuvo, D.Chengyu and S.K.Mitra., " Interpolated Finite Impulse Response Filters", IEEE Trans. ASSP, June 1984,
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B.S. Haroun and M. I. Elmasry, "Automatic Synthesis of a Multi-Bus Architecture for DSP", ICCAD, Nov 1988.
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M. Breternitz Jr and J. P. Shen, "'Architecture Synthesis of High-Performance Application-Specific Processors", CMUCAD 90- 7, Mar 1990.
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CITED BY 12
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Yaw Fann , Minjoong Rim , Rajiv Jain, Global scheduling for high-level synthesis applications, Proceedings of the 31st annual conference on Design automation, p.542-546, June 06-10, 1994, San Diego, California, United States
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