ACM Portal
  Subscribe (Full Service)    Register (Limited Service, Free)    Login
  Search:   The ACM Digital Library   The Guide
  
ACM Home Page
Please provide us with feedback. Feedback
Proofs: a fast, memory efficient sequential circuit fault simulator
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 27th ACM/IEEE Design Automation Conference table of contents
Orlando, Florida, United States
Pages: 535 - 540  
Year of Publication: 1991
ISBN:0-89791-363-9
Authors
Thomas M. Niermann
Wu-Tung Cheng
Janak H. Patel
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): n/a,   Downloads (12 Months): n/a,   Citation Count: 21
Additional Information:

abstract   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/123186.123396
What is a DOI?

ABSTRACT

This paper describes PROOFS, a super fast fault simulator for synchronous sequential circuits. PROOFS achieves high performance by combining all the advantages of differential fault simulation, single fault propagation, and parallel fault simulation, while minimizing their individual disadvantages. PROOFS minimizes the memory requirements, reduces the number of events that need to be evaluated, and simplifies the complexity of the software implementation. PROOFS requires an average of one fifth the memory required for concurrent fault simulation and runs 6 to 67 times faster on the ISCAS sequential benchmarks.


CITED BY  21
Paul G. Ryan , W. Kent Fuchs , Irith Pomeranz, Fault dictionary compression and equivalence class computation for sequential circuits, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.508-511, November 07-11, 1993, Santa Clara, California, United States
D. H. Lee , S. M. Reddy, On efficient concurrent fault simulation for synchronous sequential circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.327-331, June 08-12, 1992, Anaheim, California, United States
Indradeep Ghosh , Niraj K. Jha , Sudipta Bhawmik, A BIST scheme for RTL controller-data paths based on symbolic testability analysis, Proceedings of the 35th annual conference on Design automation, p.554-559, June 15-19, 1998, San Francisco, California, United States
Indradeep Ghosh , Anand Raghunathan , Niraj K. Jha, Hierarchical test generation and design for testability of ASPPs and ASIPs, Proceedings of the 34th annual conference on Design automation, p.534-539, June 09-13, 1997, Anaheim, California, United States
Aiman El-Maleh , Thomas Marchok , Janusz Rajski , Wojciech Maly, On test set preservation of retimed circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.176-182, June 12-16, 1995, San Francisco, California, United States
H. K. Lee , D. S. Ha, HOPE: an efficient parallel fault simulator for synchronous sequential circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.336-340, June 08-12, 1992, Anaheim, California, United States
E. Vandris , G. Sobelman, Algorithms for fast, memory efficient switch-level fault simulation, Proceedings of the 28th conference on ACM/IEEE design automation, p.138-143, June 17-22, 1991, San Francisco, California, United States
Yoshihiro Kitamura, Sequential circuit fault simulation by fault information tracing algorithm: FIT, Proceedings of the 28th conference on ACM/IEEE design automation, p.151-154, June 17-22, 1991, San Francisco, California, United States
Takaharu Nagumo , Masahiko Nagai , Takao Nishida , Masayuki Miyoshi , Shunsuke Miyamoto, VFSIM: vectorized fault simulator using a reduction technique excluding temporarily unobservable faults, Proceedings of the 31st annual conference on Design automation, p.510-515, June 06-10, 1994, San Diego, California, United States
Hyung Ki Lee , Dong Sam Ha, New methods of improving parallel fault simulation in synchronous sequential circuits, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.10-17, November 07-11, 1993, Santa Clara, California, United States
Mehrdad Mojtahedi , Walter Geisselhardt, New methods for parallel pattern fast fault simulation for synchronous sequential circuits, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.2-5, November 07-11, 1993, Santa Clara, California, United States
R. K. Roy , A. Chatterjee , J. H. Patel , J. A. Abraham , M. A. d'Abreu, Automatic test generation for linear digital systems with bi-level search using matrix transform methods, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.224-228, November 1992, Santa Clara, California, United States
Thomas Niermann , Janak H. Patel, HITEC: a test generation package for sequential circuits, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
Irith Pomeranz , Sudhakar M. Reddy, On Fault Simulation for Synchronous Sequential Circuits, IEEE Transactions on Computers, v.44 n.2, p.335-340, February 1995
Erwin Trischler , Mats Johansson, Ten: A Concurrent Test Engineering Environment, IEEE Design & Test, v.11 n.3, p.6-16, July 1994
Indradeep Ghosh , Srivaths Ravi, On automatic generation of RTL validation test benches using circuit testing techniques, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
Srivaths Ravi , Ganesh Lakshminarayana , Niraj K. Jha, TAO: regular expression-based register-transfer level testability analysis and optimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.824-832, 12/1/2001
Thomas E. Marchok , Aiman El-Maleh , Janusz Rajski , Wojciech Maly, Testability Implications of Performance-Driven Logic Synthesis, IEEE Design & Test, v.12 n.2, p.32-39, June 1995
Yiorgos Makris , Jamison Collins , Alex Orailoğlu, Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface, Journal of Electronic Testing: Theory and Applications, v.18 n.1, p.29-42, February 2002
Yiorgos Makris , Alex Orailoǧlu, RTL Test Justification and Propagation Analysis for Modular Designs, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.105-120, Oct. 1998
T. E. Marchok , A. El-Maleh , W. Maly , J. Rajski, Complexity of sequential ATPG, Proceedings of the 1995 European conference on Design and Test, p.252, March 06-09, 1995

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Sequential circuits

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)
      B.7.3 Reliability and Testing**
          Subjects: Test generation**


General Terms:
Algorithms, Design, Reliability

Collaborative Colleagues:
Thomas M. Niermann: colleagues
Wu-Tung Cheng: colleagues
Janak H. Patel: colleagues

The ACM Portal is published by the Association for Computing Machinery. Copyright © 2009 ACM, Inc.
Terms of Usage   Privacy Policy   Code of Ethics   Contact Us

Useful downloads: Adobe Acrobat    QuickTime    Windows Media Player    Real Player