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LECSIM: a levelized event driven compiled logic simulation
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 27th ACM/IEEE Design Automation Conference table of contents
Orlando, Florida, United States
Pages: 491 - 496  
Year of Publication: 1991
ISBN:0-89791-363-9
Authors
Zhicheng Wang  Department of Computer Science and Engineering, University of South Florida, Tampa, FL
Peter M. Maurer  Department of Computer Science and Engineering, University of South Florida, Tampa, FL
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 11,   Downloads (12 Months): 30,   Citation Count: 13
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ABSTRACT

LECSIM is a highly efficient logic simulator which integrates the advantages of event driven interpretive simulation and levelized compiled simulation. Two techniques contribute to the high efficiency. First it employs the zero-delay simulation model with levelized event scheduling to eliminate most unnecessary evaluations. Second, it compiles the central event scheduler into simple local scheduling segments which reduces the overhead of event scheduling. Experimental results show that LECSIM runs about 8-77 time faster than traditional unit-delay event-driven interpretive simulator. LECSIM also provides the option of scheduling with respect to individual gates or with respect to fan-out free blocks. When the circuit is partitioned into fan-out free blocks, the speed increases by a factor of 2-3. With partitioning, the speed of LECSIM is only about 1.5-3.4 times slower than a levelized compiled simulation for the combinational circuits we have tested.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
M. A. Breuer, A. D. Frieclman, Diagnosis and Reliable De.sign of Digital Systems, Computer Science Press, Woodland Hills, CA, 1976.
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S. Gai, F. Somenzi, M. Spalla, "Fast and Coherent Simulation with Zero Delay Elements," IEEE Trans. on Computer-Aided Design, Vol. 6, No. 1, Jan., 1987, pp.85- 91.
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Z. Barzilai, D. K. Beece, L. M. Huisman, V. S. Iyengar, G. M. Silberman, "SLS-A Fast Switch-Level Simulator," IEEE Trans. on Computer-Aided Design, Vo}L. 7, No. 8, August, 1988, pp. 838-49.
 
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Z. Barzilai, I. L. Carter. B. K. Rosen, J. D. Rutledge, "HSS-A High-Speed Simulator," IEEE Trans. on Computer- Aided Design, Vol. 6, No. 4, July, 1987, pp. 601-16.
 
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D. M. Lewis, "Hierarchical Compiled Event-Driven Logic Simulation," proceeding of ICCAD-89.
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P. M. Maurer, Z. Wang, C. D. Morency, 'Techniques for Multi-Level Compiled Simulation," University of South Florida, Department of Computer Science and Engineering Technical Report, CS E-89-04.
 
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CITED BY  13

Collaborative Colleagues:
Zhicheng Wang: colleagues
Peter M. Maurer: colleagues