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ABSTRACT

We present an automatic layout generation system, called LiB, for the library cells used in CMOS ASIC design. LiB takes a transistor-level circuit schematic in SPICE format and outputs a symbolic layout. Our layout style is similar to that proposed by Uehara and van Cleemput in [17]. We propose several heuristic algorithms to solve the transistor-clustering, -pairing, -chaining, -folding, the chain placement, the routing, and the net assignment problems, respectively. Experimental results are presented to show the capability of LiB.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout; Placement and routing

General Terms:
Design, Experimentation