An object-oriented VHDL design environment

ABSTRACT

This paper presents a System-level Design Environment(SDE) for VHDL. The object-oriented approach is used for modeling the VHDL entities, design constraints and even design patterns. We suggest the data model and its internal schema, which is suitable for the VHDL semantics. SDE allows a designer to reconfigure the designed schematic by binding its generic components to technology-specific ones. It is effectively used for version control. SDE verifies the design by dynamically checking the constraints. The standard VHDL is extended in order to represent the constraints properly.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Hardware description languages

  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

General Terms:
Algorithms, Design