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Layout compaction with attractive and repulsive constraints
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 27th ACM/IEEE Design Automation Conference table of contents
Orlando, Florida, United States
Pages: 369 - 374  
Year of Publication: 1991
ISBN:0-89791-363-9
Author
Akira Onozawa  NTT LSI Laboratories, Atsugi-shi, Kanagawa, 243-01, Japan
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 5,   Downloads (12 Months): 13,   Citation Count: 1
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ABSTRACT

A one-dimensional compaction algorithm with attractive and repulsive constraints is proposed. Depending on these constraints, the proposed algorithm shrinks[expands] the spaces among the specified layout elements without causing any design rule violations, as if some force were affecting them. It implies that the resultant layout has less cross talk and delay. The proposed network simplex algorithm experimentally proves to be efficient in both time and space.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Y.-z. Liao and (3. K. Wong, An algorithm to compact a VLSI symbolic layout with mixed constraints, IEEE Trans. Computer-Aided Desig.n, vol. CAD-2, no.2, pp.62-69, April 1983.
 
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T. Yoshimura, A graph theoretical compaction al. gorithm, in Proe. ISCAS 85, pp.1455-1458, June 1985.
 
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J. Burns and A.R. Newton, 5'PARCS:A new constraint-based IC symbolic spacer, Proc. of Custom Integrated Circuit Conference, pp.534- 539, 1986.
 
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IMSL MATH/LIBRARY USER'S MANUAL vol.3, IBM.