Delay and area optimization in standard-cell design

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Delay and area optimization in standard-cell design

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 27th ACM/IEEE Design Automation Conference table of contents

Orlando, Florida, United States

Pages: 349 - 352

Year of Publication: 1991

ISBN:0-89791-363-9

Authors

Shen Lin	Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA
M. Marek-Sadowska	Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA
Ernest S. Kuh	Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 12, Downloads (12 Months): 43, Citation Count: 14

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ABSTRACT

This paper presents a heuristic approach to the optimal selection of standard cells in VLSI circuit design. We are considering a cell library composed of several templates (3-5) for each type of cell. These templates differ in area, driving capabilities, intrinsic delay, and capacitive loading. When realizing a logically synthesized circuit, we select the best templates from the cell library to minimize the total area of the cells under delay constraints. We have found a very successful heuristic approach to attack this discrete optimization problem. Experimental results show that this approach runs very fast, with the complexity of &Ogr;(n2), and improves the results obtained from the technology mapping of misII. [15]

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 14

	Koichi Sato , Masamichi Kawarabayashi , Hideyuki Emura , Naotaka Maeda, Post-layout optimization for deep submicron design, Proceedings of the 33rd annual conference on Design automation, p.740-745, June 03-07, 1996, Las Vegas, Nevada, United States
	Weitong Chuang , Sachin S. Sapatnekar , Ibrahim N. Hajj, A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.220-223, November 07-11, 1993, Santa Clara, California, United States
	T. Mitsuhashi , M. Murakata , K. Yoshida , T. Aoki, Physical design CAD in deep sub-micron era, Proceedings of the conference on European design automation, p.350-355, September 1996, Geneva, Switzerland
	Lalgudi N. Kannan , Peter R. Suaris , Hong-Gee Fang, A methodology and algorithms for post-placement delay optimization, Proceedings of the 31st annual conference on Design automation, p.327-332, June 06-10, 1994, San Diego, California, United States
	Kerry S. Lowe , P. Glenn Gulak, A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuits, Proceedings of the conference on European design automation, p.42-47, September 19-23, 1994, Grenoble, France
	S. Kim , P. Banerjee , V. Chickermane , J. H. Patel, APT: an area-performance-testability driven placement algorithm, Proceedings of the 29th ACM/IEEE conference on Design automation, p.141-146, June 08-12, 1992, Anaheim, California, United States
	Majid Sarrafzadeh , Maogang Wang, NRG: global and detailed placement, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.532-537, November 09-13, 1997, San Jose, California, United States
	Joe G. Xi , Wayne W.-M. Dai, Useful-skew clock routing with gate sizing for low power design, Proceedings of the 33rd annual conference on Design automation, p.383-388, June 03-07, 1996, Las Vegas, Nevada, United States
	Timothy M. Burks , Karem A. Sakallah, Optimization of critical paths in circuits with level-sensitive latches, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.468-473, November 06-10, 1994, San Jose, California, United States
	Kerry S. Lowe , P. Glenn Gulak, Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.216-219, November 07-11, 1993, Santa Clara, California, United States
	Weitong Chuang , Ibrahim N. Hajj, Delay and area optimization for compact placement by gate resizing and relocation, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.145-148, November 06-10, 1994, San Jose, California, United States
	Shen Lin , Malgorzata Marek-Sadowska, A fast and efficient algorithm for determining fanout trees in large networks, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	Joe Gufeng Xi , Wayne Wei-Ming Dai, Useful-Skew Clock Routing with Gate Sizing for Low Power Design, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.163-179, June/July 1997
	Joe Gufeng Xi , Wayne Wei-Ming Dai, Useful-Skew Clock Routing with Gate Sizing for Low Power Design, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.163-179, June/July 1997