| Reduced offsets for two-level multi-valued logic minimization |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 27th ACM/IEEE Design Automation Conference
table of contents
Orlando, Florida, United States
Pages: 290 - 296
Year of Publication: 1991
ISBN:0-89791-363-9
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Authors
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Abdul A. Malik
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IBM T.J. Watson Research Center, Yorktown Heights, N.Y.
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Robert K. Brayton
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Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
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A. Richard Newton
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Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
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Alberto L. Sangiovanni-Vincentelli
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Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
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| Bibliometrics |
Downloads (6 Weeks): 2, Downloads (12 Months): 11, Citation Count: 3
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ABSTRACT
The approaches to two-level logic minimization can be classified into two groups: those that use tautology for expansion of cubes and those that use the offset. Tautology based schemes are generally slower and often give somewhat inferior results, because of a limited global picture of the way in which the cube can be expanded. If the offset is used, usually the expansion can be done quickly and in a more global way because it is easier to see effective directions of expansion. The problem with this approach is that there are many functions that have a reasonable size onset and don't care set but the offset is unreasonably large. It was recently shown that for the minimization of such Boolean functions, a new approach using reduced offsets, provides the same global picture and can be computed much faster. In this paper we extend reduced offsets to logic functions with multi-valued inputs.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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G. DeMicheli, R. K. Brayton, and A. L. Sangiovanni- Vincentelli. Optimal State Assignment of Finite State Machines. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD- 4(3):269-284, July 1985.
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S. J. Hong, R. G. Cain, and D. L. Ostapko. MINI: A Heuristic Approach for Logic Minimization. IBM Journal of Research and Development, 18:443--458, September 1974.
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B. Lin and A. Newton. Restructuring State Machines and State Assignment: Relationship to Minimizing Logic Across Latch Boundaries. In Proceedings of 2nd MCNC1nternational Workshop on Logic Synthesis, Research Triangle Park, North Carolina, May 1989.
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A. A. Malik, R. Bmyton, A. R. Newton, and A. Sangiovanni-Vincentelli. A Modified Approach to Two-Level Minimization. In Proceedings of International Conference on Computer-Aided Design, pages 106-109, Santa Clara, November 1988.
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S. Malik, R. Brayton, and A. Sangiovanni-Vincentelli. Encoding Symbolic Inputs for Multi-Level Logic Implementation. In Proceedings of 2nd MCNC International Workshop on Logic Synthesi ,J, Research Triangle Park, North Carolina, May 1989.
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R. L. Rudell. Multiple-Valued Logic Minimization for PLA Synthesis. Technical Report M86165, Electronics Research Laboratory, College of Engineering, University of California at Berkeley, Berkeley, CA 94720, 1986.
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