| Boolean resubstitution with permissible functions and binary decision diagrams |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 27th ACM/IEEE Design Automation Conference
table of contents
Orlando, Florida, United States
Pages: 284 - 289
Year of Publication: 1991
ISBN:0-89791-363-9
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Authors
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Hitomi Sato
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Semiconductor Division, FUJITSU Limited, Kawasaki, Japan
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Yoshihiro Yasue
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Semiconductor Division, FUJITSU Limited, Kawasaki, Japan
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Yusuke Matsunaga
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AI Laboratory, FUJITSU Labs. Limited, Kawasaki, Japan
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Masahiro Fujita
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AI Laboratory, FUJITSU Labs. Limited, Kawasaki, Japan
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| Bibliometrics |
Downloads (6 Weeks): 9, Downloads (12 Months): 19, Citation Count: 7
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ABSTRACT
In this paper, we present a new Boolean resubstitution technique with permissible functions and ordered binary decision diagrams, abbreviated as OBDD[8]. Boolean resubstitution is one technique for multi-level logic optimization. Permissible functions are special don't care sets. We represent the data structure of permissible functions and logic functions at each node in Boolean networks in terms of OBDD. Therefore, logic functions can be flexibly manipulated and rapidly executed. We have previously reported a multi-level logic optimization technique called transduction methods[1] using OBDD in ICCAD'89[7]. We have improved the OBDD operation techniques, so that now OBDD operations can be executed faster than we reported before. We also applied Boolean resubstitution to our multi-level logic synthesis. We present results of experiments employing the improved OBDD operation techniques and applying Boolean resubstitution to our multi-level logic synthesis.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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R.K.Brayton, R.Rudell, A.Sangiovanni-Vincentelli and A.R.Wang," MIS: Multi-level interactive logic optimization system," IEEE TC., Vol.CAD-6(6), November 1989, pp 1062-1081.
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A. Saldanha , A. R. Wang , R. K. Brayton , A. L. Sangiovanni-Vincentelli, Multi-level logic simplification using don't cares and filters, Proceedings of the 26th ACM/IEEE conference on Design automation, p.277-282, June 25-28, 1989, Las Vegas, Nevada, United States
[doi> 10.1145/74382.74429]
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D.Bostick, G.D.Hachtel, R.Jacoby, M.R.Lightner, P.Moceyunas, C.R.Morrison, D.Ravenscroft," THE BOULDER OPTIMAL LOGIC DESIGN SYSTEM," IEEE ICCAD, 1987, pp62-65.
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G.Hachtel, R.Jacoby, P.Moceyunas and C.Morrison," Performance Enhancements in BOLD using "implications"," IEEE ICCAD, November 1988, pp94-97.
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Y.Matsunaga and M. Fujita," Multi-level logic optimization using binary decision dJLagrams," IEEE ICCAD, November 1989.
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Robert K. B ray ton , " Multi- level Logic Synthesis," ICCAD-89 Tutorial, November 1989.
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CITED BY 7
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Hiroshi Sawada , Takayuki Suyama , Akira Nagoya, Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.353-358, November 05-09, 1995, San Jose, California, United States
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Masahiro Tomita , Tamotsu Yamamoto , Fuminori Sumikawa , Kotaro Hirano, Rectification of multiple logic design errors in multiple output circuits, Proceedings of the 31st annual conference on Design automation, p.212-217, June 06-10, 1994, San Diego, California, United States
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