| An optimal algorithm for floorplan area optimization |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 27th ACM/IEEE Design Automation Conference
table of contents
Orlando, Florida, United States
Pages: 180 - 186
Year of Publication: 1991
ISBN:0-89791-363-9
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Authors
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Ting-chi Wang
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Department of Computer Sciences, University of Texas at Austin, Austin, Texas
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D. F. Wong
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Department of Computer Sciences, University of Texas at Austin, Austin, Texas
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Downloads (6 Weeks): 4, Downloads (12 Months): 46, Citation Count: 22
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ABSTRACT
In this paper we present an optimal algorithm for the floorplan area optimization problem. Our algorithm is based on an extension of the technique in [5]. Experimental results indicate that our algorithm is efficient and capable of successfully handling large floorplans. We compare our algorithm with the branch-and-bound optimal algorithm in [6]. The running time of our algorithm is substantially less than that of [6]. For several examples where the algorithm in [6] ran for days and did not terminate, our algorithm produced optimal solutions in a few seconds.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Arvindam, S., V. Kum~r and V.N. Rao "Floorplan Optimization on Multiprocessors," ICC19.89.
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Lauther, U., "A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation," Journal of Digital Systems, Vol. IV, I,~sue 1 (1980), ~1- 34.
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Wimer, S., I. Koren and I. Cederbaum, "Optimal Aspect Ratios of Building Blocks in VLSI," IEEE Trans. on CAD, Vol. CAD-8, No. 2 (1989), 139-145.
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Wong, D.F. and K.S. The, "An Algorithm for Hierarchical Floorplan Design," Proc. IEEE b~ternational Conf. on Computer-Aided Design (1989), 4~4-487.
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CITED BY 22
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K. Bazargan , S. Kim , M. Sarrafzadeh, Nostradamus: a floorplanner of uncertain design, Proceedings of the 1998 international symposium on Physical design, p.18-23, April 06-08, 1998, Monterey, California, United States
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Hiroshi Murata , Kunihiro Fujiyoshi , Shigetoshi Nakatake , Yoji Kajitani, Rectangle-packing-based module placement, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.472-479, November 05-09, 1995, San Jose, California, United States
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Yun-Chih Chang , Yao-Wen Chang , Guang-Ming Wu , Shu-Wei Wu, B*-Trees: a new representation for non-slicing floorplans, Proceedings of the 37th conference on Design automation, p.458-463, June 05-09, 2000, Los Angeles, California, United States
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Shigetoshi Nakatake , Kunihiro Fujiyoshi , Hiroshi Murata , Yoji Kajitani, Module placement on BSG-structure and IC layout applications, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.484-491, November 10-14, 1996, San Jose, California, United States
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F. Y. Young , Chris C. N. Chu , W. S. Luk , Y. C. Wong, Floorplan area minimization using Lagrangian relaxation, Proceedings of the 2000 international symposium on Physical design, p.174-179, May 2000, San Diego, California, United States
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Pei-Ning Guo , Chung-Kuan Cheng , Takeshi Yoshimura, An O-tree representation of non-slicing floorplan and its applications, Proceedings of the 36th ACM/IEEE conference on Design automation, p.268-273, June 21-25, 1999, New Orleans, Louisiana, United States
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