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Timing verification using HDTV
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 27th ACM/IEEE Design Automation Conference table of contents
Orlando, Florida, United States
Pages: 118 - 123  
Year of Publication: 1991
ISBN:0-89791-363-9
Authors
Alan R. Martello  University of Pittsburgh, Pittsburgh, PA
Steven P. Levitan  University of Pittsburgh, Pittsburgh, PA
Donald M. Chiarulli  University of Pittsburgh, Pittsburgh, PA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 6,   Citation Count: 5
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ABSTRACT

In this paper, we provide an overview of a system designed for verifying the consistency of timing specifications for digital circuits. The utility of the system comes from the need to verify that existing digital components will interact correctly when placed together in a system. The system can also be used in the case of verifying specifications of unimplemented components.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Alice C. Parker & John J. Wallace, "SLIDE: An I/O Hardware Descriptive Language," IEEE Trans. on ComputersC-30 (June, 1981), 423-439.
 
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Alice C. Parker & Nohbyung Park, "Interface and I/O Protocol Descriptions," in Hardware Description Languages, Advances in CAD for VLSI#7, Elsevier, Amsterdam-New York, 111-136.
 
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john J. Wallace, "On Automatic Verification of SLIDE Descriptions," Design Research Center, Carnegie-Mellon University, DRC-01-2-80, Pittsburgh, PA, Aug., 1979.
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Gregor V. Bochmann, "Hardware Specification with Temporal Logic: An Example," IEEE Trans. on ComputersC-31(Mar., 1982), 223-231.
 
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Ben Moszkowski, "A Temporal Logic for Multilevel Reasoning about Hardware," IEEE Computer (Feb., 1985).
 
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Philip A. Wilsey, Computer Architecture Specification with Interval Temporal Logic, University of Cincinnati, Dept. of Elec. and Comp. Engineering, May 10, 1989.
 
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M. Browne, E. Clarke, D. Dill & B. Mishra, "Automatic Verification of Sequential Circuits Using Temporal Logic," Dept. of Computer Science, Carnegie-Mellon University, CMU-CS-85- 100, Pittsburgh, PA, Dec., 1984.
 
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E. M. Clarke, D. E. Long & K. L. McMillan, "A Language for Compositional Specification and Verification of Finite State Hardware Controllers," Carnegie-Mellon University, Computer Science Dept., CMU-CS-89-110, Jan., 1989.
 
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J. A. Nestor & D. E. Thomas, "Behavioral Synthesis with Interfaces," Proc. 1986 Inter. Conf. for Computer-Aided Design(Nov., 1986).
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Gaetano Borriello & Randy It. Katz, "Synthesis and Optimization of Interface Transducer Logic," Proc. 1987 Inter. Conf. for Computer-Aided Design (Nov., 1987).
 
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Gaetano Borriello, "Combining Event and Data- Flow Graphs in Behavioral Syhtnesis," Proc. 1988 Inter. Conf. for Computer-Aided Design(Nov., 1988).
 
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Tod Amon, Gaetano Borriello, Wayne Wilder Carlo S~quin, "A Unified Behavioral / Structural Representation for Simulation and Synthesis," Northwest Lab. for integrated Systems, University of Washington, LIS Tit 89-30-03, Nov. 1, 1989.
 
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Teresa H.-Y. Meng, Robert W. Brodersen & David G. Messerschmitt, "Automatic Synthesis of Asynchronous Circuits from High-Level Specifications," IEEE Trans. on Comp.-Aided Design8 (Nov., 1989), 1185-1205.
 
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Tomohiro Yoneda, Kazutoshi N akade & Yoshihiro Tohma, "A Fast Timing Verification Method Based on the Independence of Units," Proc. Fault Tolerant Computing Systems (1989).
 
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A. LaPaugh & D. Doukas, "Timing Verification," in Princeton Project on Digital Design, Andrea S. LaPaugh & Richard j. Lipton, eds., Computer Science Dept., Princeton University, Oct. 31, 1989, 2-3.
 
27
Texas Instruments, The Bipolar Microcomputer Components Data Book for Design Engineers, 1981.
 
28
Charles L. Seitz, "System Timing," in introduction to VLSI Systems, Carver Mead & Lynn Conway, eds., Addison Wesley, Reading, MA, 1980, 245.


Collaborative Colleagues:
Alan R. Martello: colleagues
Steven P. Levitan: colleagues
Donald M. Chiarulli: colleagues