Timing driven placement using complete path delays

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Timing driven placement using complete path delays

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 27th ACM/IEEE Design Automation Conference table of contents

Orlando, Florida, United States

Pages: 84 - 89

Year of Publication: 1991

ISBN:0-89791-363-9

Authors

Wilm E. Donath	IBM Corporation, Thomas J. Watson Research Center, Yorktown Heights, New York and Data Systems Division, Kingston, New York
Reini J. Norman	IBM Corporation, Thomas J. Watson Research Center, Yorktown Heights, New York and Data Systems Division, Kingston, New York
Bhuwan K. Agrawal	IBM Corporation, Thomas J. Watson Research Center, Yorktown Heights, New York and Data Systems Division, Kingston, New York
Stephen E. Bello	IBM Corporation, Thomas J. Watson Research Center, Yorktown Heights, New York and Data Systems Division, Kingston, New York
Sang Yong Han	IBM Corporation, Thomas J. Watson Research Center, Yorktown Heights, New York and Data Systems Division, Kingston, New York
Jerome M. Kurtzberg	IBM Corporation, Thomas J. Watson Research Center, Yorktown Heights, New York and Data Systems Division, Kingston, New York
Paul Lowy	IBM Corporation, Thomas J. Watson Research Center, Yorktown Heights, New York and Data Systems Division, Kingston, New York
Roger I. McMillan	IBM Corporation, Thomas J. Watson Research Center, Yorktown Heights, New York and Data Systems Division, Kingston, New York

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 31, Citation Count: 34

Additional Information:

abstract references cited by index terms collaborative colleagues

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ABSTRACT

The Timing Drive Placement (TDP) system balances wirability and timing constraints so that the final released design meets timing criteria. This is achieved by dynamically evaluating the timing of critical paths during placement. TDP is significant because convergence to a timed wirable solution early in the physical design cycle is achieved, or else it becomes apparent that logic changes are required.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 34

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	Vi Cuong Chan , David M. Lewis, Area-speed tradeoffs for hierarchical field-programmable gate arrays, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.51-57, February 11-13, 1996, Monterey, California, United States
	Jacques Benkoski , Andrzej J. Strojwas, The role of timing verification in layout synthesis, Proceedings of the 28th conference on ACM/IEEE design automation, p.612-619, June 17-22, 1991, San Francisco, California, United States
	Michael Hutton , Khosrow Adibsamii , Andrew Leaver, Timing-driven placement for hierarchical programmable logic devices, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.3-11, February 2001, Monterey, California, United States
	Wilm Donath , Prabhakar Kudva , Leon Stok , Lakshmi Reddy , Andrew Sullivan , Kanad Chakraborty , Paul Villarrubia, Transformational placement and synthesis, Proceedings of the conference on Design, automation and test in Europe, p.194-201, March 27-30, 2000, Paris, France
	Andrew Lim , Siu-Wing Cheng , Ching-Ting Wu, Performance oriented rectilinear Steiner trees, Proceedings of the 30th international conference on Design automation, p.171-176, June 14-18, 1993, Dallas, Texas, United States
	Jason Cong , Kwok-Shing Leung, Optimal wiresizing under the distributed Elmore delay model, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.634-639, November 07-11, 1993, Santa Clara, California, United States
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	Jen-Pin Weng , Alice C. Parker, 3D scheduling: high-level synthesis with floorplanning, Proceedings of the 28th conference on ACM/IEEE design automation, p.668-673, June 17-22, 1991, San Francisco, California, United States
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	Yasushi Ogawa , Tsutomu Itoh , Yoshio Miki , Tatsuki Ishii , Yasuo Sato , Reiji Toyoshima, Timing- and constraint-oriented placement for interconnected LSIs in mainframe design, Proceedings of the 28th conference on ACM/IEEE design automation, p.253-258, June 17-22, 1991, San Francisco, California, United States
	Kenneth D. Boese , Andrew B. Kahng , Gabriel Robins, High-performance routing trees with identified critical sinks, Proceedings of the 30th international conference on Design automation, p.182-187, June 14-18, 1993, Dallas, Texas, United States
	Amir H. Ajami , Massoud Pedram, Post-layout timing-driven cell placement using an accurate net length model with movable Steiner points, Proceedings of the 2001 conference on Asia South Pacific design automation, p.595-600, January 2001, Yokohama, Japan
	J. Frankle, Iterative and adaptive slack allocation for performance-driven layout and FPGA routing, Proceedings of the 29th ACM/IEEE conference on Design automation, p.536-542, June 08-12, 1992, Anaheim, California, United States
	Ikuo Harada , Hitoshi Kitazawa, A global router optimizing timing and area for high-speed bipolar LSI's, Proceedings of the 31st annual conference on Design automation, p.177-181, June 06-10, 1994, San Diego, California, United States
	Kiarash Bazargan , Abhishek Ranjan , Majid Sarrafzadeh, Fast and accurate estimation of floorplans in logic/high-level synthesis, Proceedings of the 10th Great Lakes symposium on VLSI, p.95-100, March 02-04, 2000, Chicago, Illinois, United States
	Kenneth D. Boese , Andrew B. Kahng , Bernard A. McCoy , Gabriel Robins, Rectilinear Steiner trees with minimum Elmore delay, Proceedings of the 31st annual conference on Design automation, p.381-386, June 06-10, 1994, San Diego, California, United States
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	Mattan Kamon , Steve McCormick , Ken Sheperd, Interconnect parasitic extraction in the digital IC design methodology, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.223-231, November 07-11, 1999, San Jose, California, United States
	Weitong Chuang , Ibrahim N. Hajj, Delay and area optimization for compact placement by gate resizing and relocation, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.145-148, November 06-10, 1994, San Jose, California, United States
	Andrew B. Kahng , Xu Xu, Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Shyam Ramji , Nagu R. Dhanwada, Design topology aware physical metrics for placement analysis, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Michael Hutton , Khosrow Adibsamii , Andrew Leaver, Adaptive delay estimation for partitioning-driven PLD placement, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.60-63, February 2003
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	Shamik Das , Anantha Chandrakasan , Rafael Reif, Timing, energy, and thermal performance of three-dimensional integrated circuits, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Haoxing Ren , David Z. Pan , David S. Kung, Sensitivity guided net weighting for placement driven synthesis, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Ting-Yuan Wang , Jeng-Liang Tsai , Charlie Chung-Ping Chen, Sensitivity guided net weighting for placement driven synthesis, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Qinghua Liu , Bo Hu , Malgorzata Marek-Sadowska, Individual wire-length prediction with application to timing-driven placement, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.10, p.1004-1014, October 2004
	Cristinel Ababei , Navaratnasothie Selvakkumaran , Kia Bazargan , George Karypis, Multi-objective circuit partitioning for cutsize and path-based delay minimization, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.181-185, November 10-14, 2002, San Jose, California
	Tao Luo , David Newmark , David Z. Pan, A new LP based incremental timing driven placement for high performance designs, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
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