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A linear program driven scheduling and allocation method followed by an interconnect optimization algorithm
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 27th ACM/IEEE Design Automation Conference table of contents
Orlando, Florida, United States
Pages: 77 - 83  
Year of Publication: 1991
ISBN:0-89791-363-9
Authors
C. A. Papachristou  Computer Engineering Department, Case Western Reserve University, Cleveland, Ohio
H. Konuk  CAD Language Systems, Inc., 15245 Shady Grove RD, Rockville, MD
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 7,   Downloads (12 Months): 17,   Citation Count: 14
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ABSTRACT

A new method for high level synthesis is reported whose basic feature is the tight interaction and coupling of the scheduling and allocation phases providing a global direction to synthesis. A linear program based allocation is proposed which uses multifunction ALU cost estimation, and iteratively drives a tree search for scheduling. A major contribution of this paper is a new interconnect optimization algorithm which is based on several interconnect transformations for multiplexer input collapsing and merging. Several other important synthesis aspects are included, e.g. register and interconnect bindings, operation chaining and operation multicycling. The method has been implemented in C on a Sun 3/60,


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Dantzig G.B., "Linear ProgrLmming and Extensiom", Princeton University Press, 1963.
 
2
Papachristou C., and H. Konulr, "A high level synthesis lechnique based on linear programming," 4th Intern. Workshop on High Level Synthesis, Oct. 1989, Tech. Repmt # CES-g9-21, Computer Engineering, Case Western Reserve University.
 
3
Abadir M., and M. A. Breuer, "A knowledge-based system for designing testable VLSI chips," IEEE DesigJt & Test, Vol. 2, August I985, pp. 56-68.
 
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8
Paulin P.G., J.P. Knight, "Force-Directed Scheduling for the Behavioral Synthesis of ASICs", IEEE Trans. on CAD, pp. 661-679, June 1989.
 
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12
Hafer L., A. Parker, "A Formal Method for the Specification, Analysis and Design of Register-Transfer Level Digital Logic," IEEE Trans. on CAD, Vol. CAD-2, 1983, pp. 4-18.
 
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14
Devadas S., A. Newton, "Algorithms for Hardware Allocation in Data Path Synthesis", IEEE Trans. on CAD, pp. 768-81 July 1989.
 
15
Prasad K.S., C. Eswaran, "I/mit-Cycle Free Complex Biquad Recursive Digital Filters', IEEE Tra,s. Circuits and Systems, Feb. 1989.
 
16
Turner L.E., B.K. Rame~h, "Low Sensitivity Digital Ladder Fi}ten with Elliptic Magnitude Response", IEF~ Traits. on Circuits and Systems, pp. 697-706, luly 1986.
 
17
Jain R., MJ. Mlinar, A.C. Parker, "Area-Time Model for Synthesis of Non-Pipelined D~igns', ICCAD-88, Nove. 1988, pp. 48-51.

CITED BY  14

Collaborative Colleagues:
C. A. Papachristou: colleagues
H. Konuk: colleagues