The VHDL validation suite

ABSTRACT

A validation suite for IEEE standard VHDL is discussed along with its executive manager. Test points are generated from the VHDL LRM (Language Reference Manual) syntax diagrams and sentences. Each test in the suite contains a test header which is specially formatted and keeps information such as test point, test objective, test result, and test type. The suite executive manager is menu-driven and efficiently classifies the tests based on different criterion defined in the test header. Coverage is defined to measure how closely a VHDL tool covers the LRM and is also computed by the suite executive manager.

REFERENCES

• 1: User's Manual For The Standard VHDL 1076 Support Environment, Document Number IR-MD-103-3, Intermetrics, Inc., Aug. 1988.
• 2: Vantage Spread Sheet Analyst User's Guide, Document Number 003, Vantage Analysis Systems, Inc., June 1989.
• 3: MCC CAD VHDL System (Version 1.1) User's Guide, Technical Report Number CAD-207-89 (O), MCC, 1989.
• 4: VHDL Analyzer User's Manual for VAXNMS, DN 0257-5, CAD Language Systems, Inc., Aug. 1989.
• 5: IEEE Standard VHDL Language Reference Manual, IEEE, Inc., New York, NY, March 1988.
• 6: 1978 Fortran Compiler Validation System User's Guide (FCVS 78) - Version 2 Release 0, Federal Software Testing Center, Dec. 1982.
• 7: Brian A. Wichmann , Z. J. Ciechanowicz, Pascal Compiler Validation, John Wiley & Sons, Inc., New York, NY, 1983
• 8: J. B. Goodenough, "The Ada Compiler Validation Capability', Computer, pp. 57-64, June 1981.
• 9: The Ada Compiler Validation Capability User's Guide (ACVC Version 1.t0), SofTech, Inc., Dec. 1987.
• 10: James R. Armstrong, Chip-level modeling with VHDL, Prentice-Hall, Inc., Upper Saddle River, NJ, 1988
• 11: David R. Coelho, The VHDL Handbook, Kluwer Academic Publishers, Norwell, MA, 1989
• 12: Roger Lipsett , Cary A. Ussery , Carl F. Schaefer, VHDL, Hardware Description and Design, Kluwer Academic Publishers, Norwell, MA, 1993
• 13: C. H. Cho, S. R. Shah, and J. R. Armstrong, VHDL LRM Test Points, Department of Electrical Engineering, Virginia Tech, April 1989.
• 14: J.R. Armstrong, C. H. Cho, and S. R. Shah, The VHDL Validation Suite Test Development Manual, Department of Electrical Engineering, Virginia Tech, March 1989.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Hardware description languages

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Hardware description languages

  D. Software
  D.2 SOFTWARE ENGINEERING
      D.2.4 Software/Program Verification
          Subjects: Validation

General Terms:
Design, Languages, Standardization, Verification