Compilation for explicitly managed memory hierarchies

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Compilation for explicitly managed memory hierarchies

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Principles and Practice of Parallel Programming archive
Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming table of contents

San Jose, California, USA

SESSION: Compilation, performance, and energy table of contents

Pages: 226 - 236

Year of Publication: 2007

ISBN:978-1-59593-602-8

Authors

Timothy J. Knight	Stanford University, Stanford, CA
Ji Young Park	Stanford University, Stanford, CA
Manman Ren	Stanford University, Stanford, CA
Mike Houston	Stanford University, Stanford, CA
Mattan Erez	Stanford University, Stanford, CA
Kayvon Fatahalian	Stanford University, Stanford, CA
Alex Aiken	Stanford University, Stanford, CA
William J. Dally	Stanford University, Stanford, CA
Pat Hanrahan	Stanford University, Stanford, CA

Sponsors

ACM: Association for Computing Machinery
SIGPLAN: ACM Special Interest Group on Programming Languages

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ACM New York, NY, USA

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Downloads (6 Weeks): 13, Downloads (12 Months): 99, Citation Count: 8

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ABSTRACT

We present a compiler for machines with an explicitly managed memory hierarchy and suggest that a primary role of any compiler for such architectures is to manipulate and schedule a hierarchy of bulk operations at varying scales of the application and of the machine. We evaluate the performance of our compiler using several benchmarks running on a Cell processor.

REFERENCES

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	Roger D. Chamberlain , Joseph M. Lancaster , Ron K. Cytron, Visions for application development on hybrid computing systems, Parallel Computing, v.34 n.4-5, p.201-216, May, 2008
	Tarik Saidani , Stéphane Piskorski , Lionel Lacassagne , Samir Bouaziz, Parallelization schemes for memory optimization on the cell processor: a case study of image processing algorithm, Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, p.9-16, September 16-16, 2007, Brasov, Romania
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