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Compact FPGA implementations of QUAD
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Source ASIAN ACM Symposium on Information, Computer and Communications Security archive
Proceedings of the 2nd ACM symposium on Information, computer and communications security table of contents
Singapore
SESSION: Short papers table of contents
Pages: 347 - 349  
Year of Publication: 2007
ISBN:1-59593-574-6
Authors
David Arditti  France Telecom R&D, France
Côme Berbain  France Telecom R&D, France
Olivier Billet  France Telecom R&D, France
Henri Gilbert  France Telecom R&D, France
Sponsor
SIGSAC: ACM Special Interest Group on Security, Audit, and Control
Publisher
ACM  New York, NY, USA
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ABSTRACT

QUAD [1] is a stream cipher whose provable security relies on the hardness of solving systems of multivariate quadratic equations. This paper explores FPGA implementations of this stream cipher and, more specifically, small area ones. The smallest of our implementations of QUAD requires only 85 slices (2961 GE) on a Virtex 4 Xilinx FPGA, which makes it not only the smallest provably secure stream cipher, but also a very good competitor among conventional stream ciphers: this implementation of QUAD's underlying PRNG results in a 68% improvement over the smallest known AES implementation on FPGA [4].


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
C. Berbain, H. Gilbert, and J. Patarin. QUAD: A Practical Stream Cipher with Provable Security. In S. Vaudenay, editor, Advances in Cryptology -- EUROCRYPT 2006, Lecture Notes in Computer Science. Springer-Verlag, 2006.
 
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4
P. Chodowiec and K. Gaj. Very Compact FPGA Implementation of the AES Algorithm. In C. D. Walter, Çetin Kaya Koç, and C. Paar, editors, Cryptographic Hardware and Embedded Systems -- CHES 2003, volume 2779 of Lecture Notes in Computer Science, pages 319--333. Springer, 2003.
 
5
ECRYPT. Web page of the eSTREAM project: http://www.ecrypt.eu.org/stream/.
 
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T. Good and M. Benaissa. Aes on fpga from the fastest to the smallest. In J. R. Rao and B. Sunar, editors, Cryptographic Hardware and Embedded Systems -- CHES 2005, volume 3659 of Lecture Notes in Computer Science, pages 427--440. Springer, 2005.
 
8
T. Good, W. Chelton, and M. Benaissa. Review of Stream Cipher Candidates from a Low Resource Hardware Perspective. Stream Ciphers Revisited -- SASC 2006, Workshop record, 2006.

Collaborative Colleagues:
David Arditti: colleagues
Côme Berbain: colleagues
Olivier Billet: colleagues
Henri Gilbert: colleagues