A fast clock scheduling for peak power reduction in LSI

ABSTRACT

The reduction of the peak power consumption of LSI is required to reduce the instability of gate operation, the delay increase, the noise and etc. It is possible to reduce the peak power consumption by clock scheduling because it controls the switching timings of registers and combinational logic elements. In this paper, we propose a fast power estimation method for the clock scheduling and fast clock scheduling methods for the peak power reduction. In experiments, it is shown that the peak power wave estimated by the proposed method in a few seconds is highly correlated with the peak power wave obtained by HSPICE simulation in several days. By using the proposed power estimation method, the proposed clock scheduling method finds clock schedules for benchmark circuits that greatly reduce the peak power in a few minutes.

REFERENCES

• 1: Atsushi Takahashi, Practical Fast Clock-Schedule Design Algorithms*The preliminary version was presented at [1]., IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E89-A n.4, p.1005-1011, April 2006 [doi>10.1093/ietfec/e89-a.4.1005]
• 2: R. B. Deoker and S. S. Sapatneker. A Graph-Theoretic Approach to Clock Skew Optimization. In ISCAS, pages 407--410, 1994.
• 3: John P. Fishburn, Clock Skew Optimization, IEEE Transactions on Computers, v.39 n.7, p.945-951, July 1990 [doi>10.1109/12.55696]
• 4: K. Kurokawa, T. Yasui, Y. Matsumura, M. Toyonaga, and A. Takahashi. A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling. IEICE Trans. Fundamentals, E85-A(12):2746--2755, 2002.
• 5: Wai-Ching Douglas Lam , Cheng-Kok Koh , Chung-Wen Albert Tsao, Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy, Proceedings of the 4th International Symposium on Quality Electronic Design, p.327, March 24-26, 2003
• 6: A. Takahashi and Y. Kajitani. Performance and reliability driven clock scheduling of sequential logic circuits. In ASP-DAC'97, pages 37--43, 1997.
• 7: P. Vuillod , L. Benini , A. Bogliolo , G. De Micheli, Clock skew optimization for peak current reduction, Proceedings of the 1996 international symposium on Low power electronics and design, p.265-270, August 12-14, 1996, Monterey, California, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Optimization

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Simulation
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Algorithms, Design, Performance

Keywords:
clock scheduling, general-synchronous framework, peak power reduction, power consumption estimation