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Efficient pipelining for modular multiplication architectures in prime fields
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Source Great Lakes Symposium on VLSI archive
Proceedings of the 17th ACM Great Lakes symposium on VLSI table of contents
Stresa-Lago Maggiore, Italy
SESSION: Arithmetic and coding table of contents
Pages: 534 - 539  
Year of Publication: 2007
ISBN:978-1-59593-605-9
Authors
Nele Mentens  Katholieke Universiteit Leuven, Heverlee (Leuven), Belgium
Kazuo Sakiyama  Katholieke Universiteit Leuven, Heverlee (Leuven), Belgium
Bart Preneel  Katholieke Universiteit Leuven, Heverlee (Leuven), Belgium
Ingrid Verbauwhede  Katholieke Universiteit Leuven, Heverlee (Leuven), Belgium
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation of the Montgomery algorithm, a more compact pipelined version is derived. The design makes use of 16-bit integer multiplication blocks that are available on recently manufactured FPGAs. The critical path is optimized by omitting the exact computation of intermediate results in the Montgomery algorithm using a 6-2 carry-save notation. This results in a high-speed architecture,which outperforms previously designed Montgomery multipliers. Because a very popular application of Montgomery multiplication is public key cryptography, we compare our implementation to the state-of-the-art in Montgomery multipliers on the basis of performance results for 1024-bit RSA.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Nele Mentens: colleagues
Kazuo Sakiyama: colleagues
Bart Preneel: colleagues
Ingrid Verbauwhede: colleagues