Block placement to ensure channel routability

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Block placement to ensure channel routability

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Great Lakes Symposium on VLSI archive
Proceedings of the 17th ACM Great Lakes symposium on VLSI table of contents

Stresa-Lago Maggiore, Italy

POSTER SESSION: Poster session 2 table of contents

Pages: 465 - 468

Year of Publication: 2007

ISBN:978-1-59593-605-9

Authors

Shigetoshi Nakatake	University of Kitakyushu, Kitakyushu, Japan
Zohreh Karimi	University of California: Los Angeles, Los Angeles, CA
Taraneh Taghavi	University of California: Los Angeles, Los Angeles, CA
Majid Sarrafzadeh	University of California: Los Angeles, Los Angeles, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery

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ACM New York, NY, USA

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ABSTRACT

Given a set of placed blocks, we present an algorithm that minimally spaces the blocks to ensure routability under several assumptions. By performing a binary search on total width/height of the chip and optimal routing area can be obtained. The proposed technique utilizes a piecewise linear model of the channel width. Based on this model, we introduce LP formulation to determine the optimal channel width considering pin alignment by balancing the wire length and the channel width.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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