Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density

ABSTRACT

This paper presents a new approach for assessing the reliability of nanometer-scale devices prior to fabrication and a practical reliability architecture realization. A four-layer architecture exhibiting a large immunity to permanent as well as random failures is used. Characteristics of the averaging/thresholding layer are emphasized. A complete tool based on Monte Carlo simulation for a-priori functional fault tolerance analysis was used for analysis of distinctive cases and topologies. A full chip CMOS integrated design of the 128-bit AES cryptography algorithm with multiple cores that incorporate reliability architectures is shown.

REFERENCES

• 1: J. von Neumann, Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components, Automata Studies, Princeton University Press, 1956.
• 2: S. Roy and V. Beiu, Multiplexing Schemes for Cost-Effective Fault-Tolerance, 4th IEEE Conference on Nanotechnology (IEEE-NANO), pp. 589--592, Aug. 2004.
• 3: Alexandre Schmid , Yusuf Leblebici, Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.11, p.1156-1166, November 2004 [doi>10.1109/TVLSI.2004.836292]
• 4: M. Stanisavljevic, A. Schmid, and Y. Leblebici, A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on A-Priori Functional Fault-Tolerance Analysis, Proc. IEEE IFIP VLSI-SoC, October 2005.
• 5: M. Stanisavljevic, A. Schmid, Y. Leblebici, Fault-Tolerance of R Publication obust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density, International Joint Conference on Neural Networks, July 2006.
• 6: Publicly available parameters for the IBM 90nm technology http://www-03.ibm.com/chips/asics/products/stdcell.html
• 7: T. Schafbauer, et al., Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology, 2002 Symposium on VLSI Technology, June 2002.
• 8: Advanced Encryption Standard, Federal Information Processing Standards 197 (FIPS 197), National Institute of Standards and Technology (NIST), November 2001.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Reliability

Keywords:
fault-tolerant architecture, high defect density, reliability of submicron and nanoelectronic systems