Compiler assisted architectural exploration for coarse grained reconfigurable arrays

ABSTRACT

A large number of factors influence the hardware cost and the mapping efficiency of applications on coarse grain reconfigurable architectures. This paper investigates for the first time in a unified way the four factors that are directly related with the efficiency of a coarse grain reconfigurable array architecture namely; the area the clock frequency, the scheduling efficiency and performance. An exploration framework has been build for estimating the values of the 4 a forementioned factors for different architecture alternatives. The exploration framework is composed of an existing retargetable compiler framework from which we estimate the mapping efficiency and the parametric realization of the coarse grained reconfigurable array architecture in hardware description language from which we estimate the clock frequency and the area of each architecture instance. The experiments refer to different architecture alternatives in terms of the processing elements' interconnection network, the register files' size, their number of input/output ports, and finally the available bandwidth. Totally 72 architecture scenarios have been studied revealing how each characteristic influences performance and area for efficiently make design decisions.

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INDEX TERMS

Primary Classification:
  D. Software
  D.3 PROGRAMMING LANGUAGES
      D.3.4 Processors
          Subjects: Retargetable compilers

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Array and vector processors
  C.4 PERFORMANCE OF SYSTEMS

  D. Software
  D.3 PROGRAMMING LANGUAGES
      D.3.4 Processors
          Subjects: Optimization

General Terms:
Design, Experimentation, Measurement, Performance

Keywords:
architectural exploration, coarse-grained reconfigurable arrays, modulo scheduling, reconfigurable computing