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Side-channel resistant system-level design flow for public-key cryptography
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Source Great Lakes Symposium on VLSI archive
Proceedings of the 17th ACM Great Lakes symposium on VLSI table of contents
Stresa-Lago Maggiore, Italy
POSTER SESSION: Poster session 1 table of contents
Pages: 144 - 147  
Year of Publication: 2007
ISBN:978-1-59593-605-9
Authors
Kazuo Sakiyama  Katholieke Universiteit Leuven, Leuven-Heverlee, Belgium
Elke De Mulder  Katholieke Universiteit Leuven, Leuven-Heverlee, Belgium
Bart Preneel  Katholieke Universiteit Leuven, Leuven-Heverlee, Belgium
Ingrid Verbauwhede  Katholieke Universiteit Leuven, Leuven-Heverlee, Belgium
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper, we propose a new design methodology to assess the risk for side-channel attacks, more specifically timing analysis and simple power analysis, at an early design stage. This method is illustrated with the design of an elliptic curve cryptographic processor. It also allows to evaluate the quality of countermeasures against these attacks by evaluating hamming distances for eachsignal and each register in a partial functional domain (e.g. datapath or controller). Thus a first order side-channel-resistant design can be obtained with system-level design in which the simulation can run faster than conventional HDL simulations.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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K. Okeya and T. Takagi, "A more flexible countermeasure against side channle attacks usign window method," in Proc. of CHES'03. LNCS, vol. 2779, pp. 397--410, 2003.

Collaborative Colleagues:
Kazuo Sakiyama: colleagues
Elke De Mulder: colleagues
Bart Preneel: colleagues
Ingrid Verbauwhede: colleagues