| Side-channel resistant system-level design flow for public-key cryptography |
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Great Lakes Symposium on VLSI
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Proceedings of the 17th ACM Great Lakes symposium on VLSI
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Stresa-Lago Maggiore, Italy
POSTER SESSION: Poster session 1
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Pages: 144 - 147
Year of Publication: 2007
ISBN:978-1-59593-605-9
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Downloads (6 Weeks): 7, Downloads (12 Months): 40, Citation Count: 0
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ABSTRACT
In this paper, we propose a new design methodology to assess the risk for side-channel attacks, more specifically timing analysis and simple power analysis, at an early design stage. This method is illustrated with the design of an elliptic curve cryptographic processor. It also allows to evaluate the quality of countermeasures against these attacks by evaluating hamming distances for eachsignal and each register in a partial functional domain (e.g. datapath or controller). Thus a first order side-channel-resistant design can be obtained with system-level design in which the simulation can run faster than conventional HDL simulations.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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