GALS SoC interconnect bus for wireless sensor network processor platforms

ABSTRACT

The purpose of this paper is to present a new System-on-Chip bus designed for the application specific requirements of Wireless Sensor Network (WSN) platforms. The bus is designed to support Globally Asynchronous Locally Synchronous (GALS) systems. The bus is multi-rate with delay tolerance to support Dynamic Voltage and Frequency Scaled (DVFS) sub-systems. Unlike traditional buses, the sub-systems operate as peers, rather than as master-slaves. Lowpower features include clock gating when inactive and burst transfers. The bus supports up to 255 interconnected resources.

REFERENCES

• 1: J. Andersen. Wireless Sensor Networks and Pervasive Computing presentation. University of Aarhus, 2005.
• 2: Jason Hill , Mike Horton , Ralph Kling , Lakshman Krishnamurthy, The platforms enabling wireless sensor networks, Communications of the ACM, v.47 n.6, June 2004 [doi>10.1145/990680.990705]
• 3: Vijay Raghunathan , Trevor Pering , Roy Want , Alex Nguyen , Peter Jensen, Experience with a low power wireless mobile computing platform, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA [doi>10.1145/1013235.1013322]
• 4: Jason Hill , Robert Szewczyk , Alec Woo , Seth Hollar , David Culler , Kristofer Pister, System architecture directions for networked sensors, ACM SIGOPS Operating Systems Review, v.34 n.5, p.93-104, Dec. 2000
• 5: Mikko Kohvakka , Tero Arpinen , Marko Hännikäinen , Timo D. Hämäläinen, High-performance multi-radio WSN platform, Proceedings of the second international workshop on Multi-hop ad hoc networks: from theory to reality, May 26-26, 2006, Florence, Italy [doi>10.1145/1132983.1133000]
• 6: Joseph Polastre , Robert Szewczyk , David Culler, Telos: enabling ultra-low power wireless research, Proceedings of the 4th international symposium on Information processing in sensor networks, April 24-27, 2005, Los Angeles, California
• 7: Daniel Marcos Chapiro, Globally-asynchronous locally-synchronous systems (performance, reliability, digital), 1985
• 8: ARM Limited. AMBA AXI Protocol v1.0 Specification. 2003, 2004.
• 9: Altera Corporation. Atlantic Interface. 2002.
• 10: Altera Corporation. Avalon Interface Specification. 2005.
• 11: Wade D. Peterson. WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores. OpenCores.org, 2002.
• 12: IBM. The CoreConnect Bus Architecture. 1999.
• 13: R. Hofmann, B. Drerup. Next Generation CoreConnect Processor Local Bus Architecture. Annual IEEE Int. ASIC/SOC Conference, 2002.
• 14: W. J. Bainbridge , S. B. Furber, Asynchronous Macrocell Interconnect using MARBLE, Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems, p.0122, March 30-April 02, 1998
• 15: E. Salminen, V. Lahtinen, K. Kuusilinna, T. Hamalainen. Overview of Bus-based System-on-chip Interconnections. IEEE ISCAS Int. Symp. on Circuits and Systems, vol.2:372--375, 2002.
• 16: Tyndall National Institute. www.tyndall.ie.
• 17: VTVT Group. http://www.ee.vt.edu/~ha/cell library/distribution.html.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.0 General

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.0 General

General Terms:
Design

Keywords:
GALS, SoC bus, WSN, application specific bus, low power, system on chip bus, wireless sensor network