NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits

ABSTRACT

This paper presents a predictive framework for accurate static timing analysis in UDSM VLSI circuits. As technology scales to smaller dimensions, coupling capacitances are becoming a critical factor in signal integrity analysis. Coupling capacitances contribute to the noise and play a seminalrole in determining the timing windows of a circuit. Accuratean alysis of coupling effects is indispensable for meaning fulstatic timing and signal integrity analysis. Our proposed framework presents a Directed Search technique to calculate accurate coupling effects. We performed experiments on theISCAS'85 benchmarks and present the accuracy improvement up-to 45.5% compared to existing approaches. We also show that our framework decreased cell delay look-uptable accesses up-to 64.8%. Our results present the coupling effect on static timing analysis.

REFERENCES

• 1: F. Brglez and H. Fujiwara. A neutral netlist of 10 combinatorial benchmark circuits. In ISCAS, pages 695--698, 1985.
• 2: Pinhong Chen , Desmond A. Kirkpatrick , Kurt Keutzer, Miller factor for gate-level coupling delay calculation, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
• 3: Pinhong Chen , Yuji Kukimoto , Kurt Keutzer, Refining switching window by time slots for crosstalk noise calculation, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.583-586, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774658]
• 4: Faraday Technology Corporation. UMC 90-nano Libraries. http://freelibrary.faraday-tech.com/, Nov. 2005.
• 5: D. Das, A. Shebaita, H. Zhou, Y. Ismail, and K. Killpack. FA-STAC: A framework for fast and accurate static timing analysis with coupling. In ICCD, 2006.
• 6: B. A. Davey and H. A. Priestley. Introduction to lattices and order. Cambridge, 1990.
• 7: M. Ghoneima and Y. Ismail. Accurate decoupling of coupled on-chip buses. In ISCAS, pages 4146--4149, 2005.
• 8: Andrew B. Kahng , Sudhakar Muddu , Egino Sarto, On switch factor based analysis of coupled RC interconnects, Proceedings of the 37th conference on Design automation, p.79-84, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337318]
• 9: Rajesh Kumar, Interconnect and noise immunity design for the Pentium 4 processor, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.776068]
• 10: Hanne Riis Nielson , Flemming Nielson, Bounded fixed point iteration, Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages, p.71-82, January 19-22, 1992, Albuquerque, New Mexico, United States [doi>10.1145/143165.143182]
• 11: T. Sakurai and A. R. Newton. Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas. IEEE Journal of Solid state circuits, 25:584--594, Apr. 1990.
• 12: S. S. Sapatnekar. A timing model incorporating the effect of crosstalk on delay and its application to optimal channel routing. IEEE TCAD, 2000.
• 13: Youngsoo Shin , Takayasu Sakurai, Coupling-driven bus design for low-power application-specific systems, Proceedings of the 38th conference on Design automation, p.750-753, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379059]
• 14: T. Xiao and M. Marek-Sadowska. Worst Delay Estimation in Crosstalk Aware Static Timing Analysis. In ICCD, 2000.
• 15: H. Zhou. Timing analysis with crosstalk is a fixpoint on a complete lattice. In IEEE Transactions on Computer-Aided Design, September 2003, pages 1261--1269, 2003.

INDEX TERMS

Primary Classification:
  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

General Terms:
Algorithms, Performance

Keywords:
crosstalk, modeling, static timing analysis