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Second bibliography on Cache memories
Source ACM SIGARCH Computer Architecture News archive
Volume 19 ,  Issue 4  (June 1991) table of contents
Pages: 154 - 182  
Year of Publication: 1991
ISSN:0163-5964
Author
Alan Jay Smith
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): n/a,   Downloads (12 Months): n/a,   Citation Count: 14
Additional Information:

cited by   index terms   collaborative colleagues  

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CITED BY  14
Norman P. Jouppi, Cache write policies and performance, ACM SIGARCH Computer Architecture News, v.21 n.2, p.191-201, May 1993
Pei Cao , Edward W. Felten , Anna R. Karlin , Kai Li, A study of integrated prefetching and caching strategies, ACM SIGMETRICS Performance Evaluation Review, v.23 n.1, p.188-197, May 1995
C. E. Wu , Y. Hsu , Y. -H. Liu, A Quantitative Evaluation of Cache Types for High-Performance Computer Systems, IEEE Transactions on Computers, v.42 n.10, p.1154-1162, October 1993
Kathryn S. McKinley , Olivier Temam, A quantitative analysis of loop nest locality, ACM SIGPLAN Notices, v.31 n.9, p.94-104, Sept. 1996
C.-H. Chen , A. K. Somani, A unified architectural tradeoff methodology, ACM SIGARCH Computer Architecture News, v.22 n.2, p.348-357, April 1994
A. Seznec, Decoupled sectored caches: conciliating low tag implementation cost, ACM SIGARCH Computer Architecture News, v.22 n.2, p.384-393, April 1994
Kathryn S. McKinley , Olivier Temam, Quantifying loop nest locality using SPEC'95 and the perfect benchmarks, ACM Transactions on Computer Systems (TOCS), v.17 n.4, p.288-336, Nov. 1999
Thomas M. Conte , Mary Ann Hirsch , Wen-mei W. Hwu, Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation, IEEE Transactions on Computers, v.47 n.6, p.714-720, June 1998
Saied Hosseini-Khayat, On Optimal Replacement of Nonuniform Cache Objects, IEEE Transactions on Computers, v.49 n.8, p.769-778, August 2000
Makoto Kobayashi, A cache multitasking model, ACM SIGMETRICS Performance Evaluation Review, v.20 n.2, p.27-37, Nov. 1992
Chung-Ho Chen , Arun K. Somani, Architecture Technique Trade-Offs Using Mean Memory Delay Time, IEEE Transactions on Computers, v.45 n.10, p.1089-1100, October 1996
Kartik K. Agaram , Stephen W. Keckler , Calvin Lin , Kathryn S. McKinley, Decomposing memory performance: data structures and phases, Proceedings of the 2006 international symposium on Memory management, June 10-11, 2006, Ottawa, Ontario, Canada
Sorav Bansal , Dharmendra S. Modha, CAR: Clock with Adaptive Replacement, Proceedings of the 3rd USENIX Conference on File and Storage Technologies, March 31-31, 2004, San Francisco, CA
Jelena Trajkovic , Alexander V. Veidenbaum , Arun Kejariwal, Improving SDRAM access energy efficiency for low-power embedded systems, ACM Transactions on Embedded Computing Systems (TECS), v.7 n.3, p.1-21, April 2008

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

Additional Classification:
  A. General Literature


General Terms:
Design

Collaborative Colleagues:
Alan Jay Smith: colleagues

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