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On the potential of asynchronous pipelined processors
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Source ACM SIGARCH Computer Architecture News archive
Volume 18 ,  Issue 4  (December 1990) table of contents
Pages: 27 - 34  
Year of Publication: 1990
ISSN:0163-5964
Authors
Ran Ginosar  Technion - Israel Institute of Technology, Haifa, Israel
Nick Michell  University of Utah, Dept. o.f Computer Science, 3190 Merrill Engineering Building, Salt Lake City, Utah
Publisher
ACM  New York, NY, USA
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ABSTRACT

An asynchronous version of the pipelined R3000 and DLX processors, the A3000, is being designed. Simulation was employed to investigate the potential speed-up obtainable due to the asynchronous operation. Preliminary results show up to a 64% improvement in performance.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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1. Chu, T. Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Specifications . PhD thesis, MIT, 1987.
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3. David, I., Ginosar, R., and Yoeli, M. Self-timed implementation of a reduced instruction set computer. Tech. Rep. 732, Dept. Elect. Eng., Technion, Oct., 1989.
 
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4. Ebergen, J. Translating Programs into Delay-Insensitive Circuits. PhD thesis, CWI, 1989.
 
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5. Ginosar, R., and Wolf, T. A3000: an asynchronous version of the r3000. Computer Science Department, University of Utah, in preparation.
 
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8. Martin, A. Programming in vlsi: from communicating processes to delay-insensitive circuits. In UT Year of Programming Inst. on Concurrent Programming , C. Hoare, Ed., Addison-Wesley, 1989.
 
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9. Martin, A., Burns, S., Lee, T., Borkovic, D., and Hazewindus, P. The design of an asynchronous microprocessor. Tech. Rep. CS-TR-89-02, Caltech, 1989.
 
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10. Martin, A., Burns, S., Lee, T., Borkovic, D., and Hazewindus, P. The first asynchronous microprocessor: the test results. Tech. Rep. CS-TR-89-06, Caltech, 1989.
 
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11. Miller, R. Switching Theory, Vol. 2. J. Wiley & Sons, 1965.
 
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12. Molnar, C., Fan, T., and Rosen berger, F. Synthesis of delay-insensitive modules. Journal of Distributed Computing (1986), 226-234.
 
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13. Seitz, C. System timing. In Introduction to VLSI Systems, C. Mead and L. Conway, Eds., Addison-Wesley, 1980, pp. 218-262.
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15. Wakerly, J. Book review: 'computer architecture: a quantitative approach'. Computer Architecture News 18, 2 (June 1990), 96-98.


Collaborative Colleagues:
Ran Ginosar: colleagues
Nick Michell: colleagues