ACM Home Page
Please provide us with feedback. Feedback
Economy of scale effects for large wafer fabs
Full text PdfPdf (177 KB)
Source Winter Simulation Conference archive
Proceedings of the 38th conference on Winter simulation table of contents
Monterey, California
SESSION: Semiconductor manufacturing: factory simulation table of contents
Pages: 1817 - 1820  
Year of Publication: 2006
ISBN:1-4244-0501-7
Author
Oliver Rose  Dresden University of Technology, Dresden, Germany
Sponsors
IEICE ESS : Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IIE : Institute of Industrial Engineers
ASA : American Statistical Association
IEEE-CS\DATC : The IEEE Computer Society
INFORMS-CS : Institute for Operations Research and the Management Sciences-College on Simulation
NIST : National Institute of Standards and Technology
SIGSIM: ACM Special Interest Group on Simulation and Modeling
(SCS) : The Society for Modeling and Simulation International
Publisher
Winter Simulation Conference 
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 11,   Citation Count: 0
Additional Information:

abstract   references   collaborative colleagues  

Tools and Actions: Review this Article  

ABSTRACT

In this paper, we present the results of a simulation study for semiconductor wafer fabrication facilities (wafer fabs) where we multiplied the number of tools per tool group and the number of operators. We were interested in the effects on the product cycle times when we keep the fab utilization constant while increasing the size of the tool groups by constant factors, i.e., forming so-called giga fabs. It turns out, that the drop in cycle time is considerable.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Atherton, L. and R. Atherton. 1995. Wafer Fabrication: Factory Performance and Analysis. Boston: Kluwer.
 
2
Fowler, J. and J. Robinson. 1995. Measurement and improvement of manufacturing capacities (MIMAC): Final report. Technical Report 95062861A-TR, SEMATECH, Austin, TX.
 
3
 
4
 
5
 
6
 
7
Rose, O. 2003. Comparison of Due-date Oriented Dispatch Rules in Semiconductor Manufacturing. In Proceedings of the 2003 Industrial Engineering Research Conference, May 18--20, Portland, OR.