Modeling semiconductor tools for small lotsize FAB simulations

ABSTRACT

Short cycle times are critical to the success of semiconductor manufacturing. The addition of more and more mask layers leads to higher raw process times and makes short cycle times an increasingly challenging task. One cycle time reduction possibility semiconductor manufacturers now look at is lotsize reduction. A reduction in lotsize transfers directly into lower raw process times. Modeling and simulation are key to assess opportunities and risks of such an approach. This paper looks at the implications that follow from small lotsizes for tool models used for the assessment.

REFERENCES

• 1: Bonnin, O., D. Mercier, D. Levy, M. Henry, I. Pouilloux, and E. Mastromatteo. 2003. Single-Water/Mini-Batch Approach for Fast Cycle Time in Advanced 300-mm Fab. IEEE Transactions on Semiconductor Manufacturing, 16(2), pp. 111--120.
• 2: Perkinson, T. L., P. K. McLarty, R. S. Gyurcsik, and R. K. Cavin III. 1994. Single-Wafer Cluster Tool Performance: An Analysis of Throughput. IEEE Transactions on Semiconductor Manufacturing, 7(3), pp. 369--373.
• 3: Pettinato, J., and D. Pilai. 2004. Technology decisions to Minimize 450mm Wafer Size Transition Risk. In Proceedings of the 2004 ISSM Conference.
• 4: Wakabayashi, T., S. Watanabe, Y. Kobayashi, T. Okabe, and A. Koike. 2004. High-Speed AMHS and Its Operation Method for 300mm QTAT Fab. IEEE Transactions on Semiconductor Manufacturing, 17(3), pp. 25--28.
• 5: Wood, S. C., S. Tripthi, and F. Moghadam. 1994. A Generic Model for Cluster Tool Throughput Time and Capacity. In Proceedings IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 194--199.
• 6: Wood, S. C. 1996. Simple Performance Models for Integrated Processing Tools. IEEE Transactions on Semiconductor Manufacturing, 9(3), pp. 320--328.