ACM Home Page
Please provide us with feedback. Feedback
Compiled code in distributed logic simulation
Full text PdfPdf (113 KB)
Source Winter Simulation Conference archive
Proceedings of the 38th conference on Winter simulation table of contents
Monterey, California
SESSION: Modeling methodology b: parallel & distributed simulation I table of contents
Pages: 981 - 986  
Year of Publication: 2006
ISBN:1-4244-0501-7
Authors
Jun Wang  McGill University, Montreal, Quebec, CANADA
Carl Tropper  McGill University, Montreal, Quebec, CANADA
Sponsors
IEICE ESS : Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IIE : Institute of Industrial Engineers
ASA : American Statistical Association
IEEE-CS\DATC : The IEEE Computer Society
INFORMS-CS : Institute for Operations Research and the Management Sciences-College on Simulation
NIST : National Institute of Standards and Technology
SIGSIM: ACM Special Interest Group on Simulation and Modeling
(SCS) : The Society for Modeling and Simulation International
Publisher
Winter Simulation Conference 
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 14,   Citation Count: 0
Additional Information:

abstract   references   collaborative colleagues  

Tools and Actions: Review this Article  

ABSTRACT

A logic simulation approach known as compiled-code eventdriven simulation was developed in the past for sequential logic simulation. It improves simulation performance by reducing the logic evaluation and propagation time. In this paper we describe the application of this approach to distributed logic simulation. Our experimental results show that using compiled code can greatly improve the stability and overall performance of a Time-Warp based logic simulator. We also present a technique called fanout aggregation that makes use of information on circuit partitions and considerably improves the run-time performance of our (distributed) compiled code simulator. It does not produce a similar improvement when used in conjunction with an interpreted simulator because of run-time overhead.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
 
2
Brglez, F., D. Bryan, and K. Kozminski. 1989. Combinational profiles of sequential benchmark circuits. In Proceedings of IEEE Symposium on Circuits and Systems.
3
4
 
5
 
6
 
7
IEEE. 2001. IEEE standard 1364--2001, IEEE standard verilog hardware description language.
8
 
9
Lee, Y., and P. Maurer. 1996, December. Bit-parallel multidelay simulation. IEEE Transactions on CAD of Integrated Circuits and Systems 15 (12): 1547--1554.
 
10
Lewis, D. 1991, June. A hierarchical compiled code event-driven logic simulator. IEEE Transactions on Computer-Aided Design 10 (6): 726--737.
 
11
 
12
Maurer, P. 1997, July. The inversion algorithm for digital simulation. IEEE Transactions on CAD of Integrated Circuits and Systems 16 (7): 762--769.
 
13
14
15