Applying parallel, dynamic-resolution simulations to accelerate VLSI power estimation

ABSTRACT

High resolution models of logic circuits need to be used in simulations to accurately track logic transitions or glitches, which contribute to the most dominant portion of VLSI power dissipated. Unfortunately, simulating large, high resolution models is a time consuming task. Although more abstract models that simulate faster can be used, they are less accurate as details of glitching activity are absent. This study proposes an alternatively approach that dynamically (i.e., during simulation) changes the resolution of a model to strike a better balance between accuracy and performance. Simulation-time resolution changes are performed using a novel methodology called Dynamic Component Substitution (DCS). This paper presents the issues involved in applying DCS to accelerate parallel power simulations of digital logic circuits. The experiments indicate that the proposed strategy can increase performance by 3x with negligible deviations in power estimates but consuming about 2x more memory.

REFERENCES

• 1: Mauro Chinosi , Roberto Zafalon , Carlo Guardiani, Parallel mixed-level power simulation based on spatio-temporal circuit partitioning, Proceedings of the 36th ACM/IEEE conference on Design automation, p.562-567, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309998]
• 2: Deng, A. 1994, April. Power analysis for cmos/bicmos circuits. In 1994 International Workshop on Low Power Design, 3--8.
• 3: Paul Eric Landman, Low-power architectural design methodologies, University of California at Berkeley, Berkeley, CA, 1995
• 4: Kangsun Lee , Paul A. Fishwick, Dynamic model abstraction, Proceedings of the 28th conference on Winter simulation, p.764-771, December 08-11, 1996, Coronado, California, United States [doi>10.1145/256562.256806]
• 5: Hao Li , Srinivas Katkoori , Wai-Kei Mak, Power minimization algorithms for LUT-based FPGA technology mapping, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.1, p.33-51, January 2004 [doi>10.1145/966137.966139]
• 6: Nagel, L. W. 1975. Spice2: A computer program to simulate semiconductor circuits. Technical report, University of California at Berkeley. Technical Report ERL-M520.
• 7: Anand Natrajan , Paul F. Reynolds, Jr. , Sudhir Srinivasan, MRE: a flexible approach to multi-resolution modeling, Proceedings of the eleventh workshop on Parallel and distributed simulation, p.156-163, June 10-13, 1997, Lockenhaus, Austria
• 8: Navabi, Z. 1995. Exemplar synthesizable pasic controller model. (available online).
• 9: David A. Patterson , John L. Hennessy, Computer organization & design: the hardware/software interface, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1993
• 10: Radharamanan Radhakrishnan , Dale E. Martin , Malolan Chetlur , Dhananjai Madhava Rao , Philip A. Wilsey, An Object-Oriented Time Warp Simulation Kernel, Proceedings of the Second International Symposium on Computing in Object-Oriented Parallel Environments, p.13-23, December 08-11, 1998
• 11: Rao, D. M. 2003. Study of dynamic component substitution. Ph.D. thesis, University of Cincinnati.
• 12: Rao, D. M., V. Chernyakhovsky, and P. A. Wilsey. 2000, January. WESE: A Web-based Environment for Systems Engineering. In 2000 International Conference On Web-Based Modelling & Simulation (WebSim' 2000). Society for Computer Simulation.
• 13: Dhananjai Madhava Rao , Philip A. Wilsey, Dynamic component substitution in web-based simulation, Proceedings of the 32nd conference on Winter simulation, December 10-13, 2000, Orlando, Florida
• 14: Dhananjai Madhava Rao , Harold W. Carter , Philip A. Wilsey, Optimizing Costs of Web-based Modeling and Simulation, Proceedings of the 15th International Parallel & Distributed Processing Symposium, p.171, April 23-27, 2001
• 15: Vanoostende, P., P. Six, J. Vandewalle, and H. J. DeMan. 1993, January. Estimation of typical power of synchronous cmos circuits using a hierarchy of simulators. IEEE journal on Solid-State Circuits 28 (1): 26--39.