A routing fabric for monolithically stacked 3D-FPGA

ABSTRACT

A previous study on the benefits of monolithically stacked 3D-FPGA has estimated a 3.2x improvement in logic density, a 1.7x improvement in delay, and a 1.7x improvement in dynamic power consumption over a baseline 2D-FPGA with no change in architecture. This paper describes a new routing fabric and shows that a 3D-FPGA using this fabric can achieve a 3.3x improvement in logic density, a 2.35x improvement in delay, and a 2.82x improvement in dynamic power consumption over the same baseline 2D-FPGA. The additional improvements in delay and power consumption are achieved by reducing net loading in several ways: (i) Only Single and Double interconnect segments are used. This reduces the total interconnect length used to implement each net. (ii) The routing fabric is hierarchical. Each logic block's inputs and outputs connect first to local segments. These segments can be then programmably connected to local segments in neighboring routing blocks via programmable buffers and/or to interconnect segments in routing channels via muxes with buffered outputs. (iii) Interconnect segments can be directly connected to form longer segments using programmable buffers without going through routing blocks. (iv) The routing block provides switching capability beyond that of a conventional switch box. A 3D-FPGA using this new routing fabric can be realized by stacking two configuration memory layers and a switch layer on top of a standard CMOS layer with a total of 12 metal layers interspersed between them. A CAD flow based on VPR with appropriate modifications to the routing graph generation and routing algorithm is developed and used in the performance analysis.

REFERENCES

• 1: A. R. Joshi and K. C. Saraswat, "Nickel induced crystallization of a-Si gate electrode at 500C and MOS capacitor reliability," IEEE Trans. Electron Devices, vol. 50, pp. 1058--1062, April 2003.
• 2: S. M. Jung, J. Jang, W. Cho, J. Moon, K. Kwak, B. Choi, B. Hwang, H. Lim, J. Jeong, J. Kim, and K. Kim, "The revolutionary and truly 3-dimensional 25F2 SRAM cell technology with the smallest S3 (Stacked Single-crystal Si) cell, 0.16um2, and SSTFT(Stacked Single-crystal Thin Film Transistor) for ultra high density SRAM," in technical digest of 2004 VLSI technology symposium, pp. 228--229, 2004.
• 3: Mingjie Lin , Abbas El Gamal , Yi-Chang Lu , Simon Wong, Performance benefits of monolithically stacked 3D-FPGA, Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA [doi>10.1145/1117201.1117219]
• 4: Vaughn Betz , Jonathan Rose , Alexander Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, Norwell, MA, 1999
• 5: Guy Lemieux , David Lewis, Circuit design of routing switches, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA [doi>10.1145/503048.503052]
• 6: V. George, Low Energy Field-Programmable Gate Array. PhD thesis, UC Berkeley, 2000.
• 7: Michael Hutton , Vinson Chan , Peter Kazarian , Victor Maruri , Tony Ngai , Jim Park , Rakesh Patel , Bruce Pedersen , Jay Schleicher , Sergey Shumarayev, Interconnect enhancements for a high-speed PLD architecture, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA [doi>10.1145/503048.503050]
• 8: David Lewis , Elias Ahmed , Gregg Baeckler , Vaughn Betz , Mark Bourgeault , David Cashman , David Galloway , Mike Hutton , Chris Lane , Andy Lee , Paul Leventis , Sandy Marquardt , Cameron McClintock , Ketan Padalia , Bruce Pedersen , Giles Powell , Boris Ratchev , Srinivas Reddy , Jay Schleicher , Kevin Stevens , Richard Yuan , Richard Cliff , Jonathan Rose, The Stratix II logic and routing architecture, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA [doi>10.1145/1046192.1046195]
• 9: Vaughn Betz , Jonathan Rose, Directional bias and non-uniformity in FPGA global routing architectures, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.652-659, November 10-14, 1996, San Jose, California, United States
• 10: Carl Ebeling , Larry McMurchie , Scott A. Hauck , Steven Burns, Placement and routing tools for the Triptych FPGA, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.4, p.473-482, Dec. 1995 [doi>10.1109/92.475966]
• 11: Li Shang , Alireza S. Kaviani , Kusuma Bathala, Dynamic power consumption in Virtex™-II FPGA family, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA [doi>10.1145/503048.503072]
• 12: Fei Li , Deming Chen , Lei He , Jason Cong, Architecture evaluation for power-efficient FPGAs, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA [doi>10.1145/611817.611844]
• 13: D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," IEEE Journal of Solid-State Circuits, vol. 29, no. 6, pp. 663--670, 1994.
• 14: E. Friedman, "Clock distribution design in VLSI circuits - an overview," in Proceedings of IEEE International Symposium on Circuits and Systems, pp. 1475--1478, May 1993.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

General Terms:
Design, Experimentation, Measurement, Performance

Keywords:
3D monolithically stacked, FPGA, performance analysis, routing architecture