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Data structures and algorithms for simplifying reversible circuits
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Source ACM Journal on Emerging Technologies in Computing Systems (JETC) archive
Volume 2 ,  Issue 4  (October 2006) table of contents
Pages: 277 - 293  
Year of Publication: 2006
ISSN:1550-4832
Authors
Aditya K. Prasad  Amazon.com Inc., Seattle, WA
Vivek V. Shende  University of Michigan, Ann Arbor, MI
Igor L. Markov  University of Michigan, Ann Arbor, MI
John P. Hayes  University of Michigan, Ann Arbor, MI
Ketan N. Patel  Qualcomm Inc., Campbell, CA
Publisher
ACM  New York, NY, USA
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ABSTRACT

Reversible logic is motivated by low-power design, quantum circuits, and nanotechnology. We develop a compact representation of small reversible circuits to generate and store optimal circuits for all 40,320 three-input reversible functions, and millions of four-input circuits. This allows implementing a function optimally in constant time for use in the peephole optimization of larger circuits produced by existing techniques, and guarantees that every three-bit subcircuit is optimal. To generate subcircuits, we use a graph-based data structure and algorithms for circuit restructuring. Finally, we demonstrate a suboptimal circuit for which peephole optimization fails.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Shende, V. V., Prasad, A. K., Markov, I. L., and Hayes, J. P. 2003. Synthesis of reversible logic circuits. IEEE Trans. Comput. Aided Des., 710--722.
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Collaborative Colleagues:
Aditya K. Prasad: colleagues
Vivek V. Shende: colleagues
Igor L. Markov: colleagues
John P. Hayes: colleagues
Ketan N. Patel: colleagues