Design space exploration for multicore architectures: a power/performance/thermal view

ABSTRACT

Multicore architectures are ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern applications, ILP diminishing returns, better thermal/power scaling (many small cores dissipate less than a large and complex one); and, ease and reuse of design.This paper presents a thorough evaluation of multicore architectures. The architecture we target is composed of a configurable number of cores, a memory hierarchy consisting of private L1 and L2, and a shared bus interconnect. We consider parallel shared memory applications. We explore the design space related to the number of cores, L2 cache size and processor complexity, showing the behavior of the different configurations/applications with respect to performance, energy consumption and temperature. Design tradeoffs are analyzed, stressing the interdependency of the metrics and design factors. In particular, we evaluate several chip floorplans. Their power/thermal characteristics are analyzed and they show the importance of considering thermal effects at the architectural level to achieve the best design choice.

REFERENCES

• 1: Cameron McNairy , Rohit Bhatia, Montecito: A Dual-Core, Dual-Thread Itanium Processor, IEEE Micro, v.25 n.2, p.10-20, March 2005 [doi>10.1109/MM.2005.34]
• 2: Poonacha Kongetira , Kathirgamar Aingaran , Kunle Olukotun, Niagara: A 32-Way Multithreaded Sparc Processor, IEEE Micro, v.25 n.2, p.21-29, March 2005 [doi>10.1109/MM.2005.35]
• 3: R. Kalla, B. Sinharoy, and J. M. Tendler. IBM Power5 Chip: A Dual-Core Multithreaded Processor. IEEE MICRO, pages 40--47, March/April 2004.
• 4: Trevor Mudge. Power: A first class constraint for future architectures. In HPCA '00: Proceedings of the 6th International Symposium on High-Performance Computer Architecture, Washington, DC, USA, 2000. IEEE Computer Society.
• 5: Kevin Skadron , Mircea R. Stan , Karthik Sankaranarayanan , Wei Huang , Sivakumar Velusamy , David Tarjan, Temperature-aware microarchitecture: Modeling and implementation, ACM Transactions on Architecture and Code Optimization (TACO), v.1 n.1, p.94-125, March 2004 [doi>10.1145/980152.980157]
• 6: Intel. White paper: Superior performance with dual-core. Technical report, Intel, 2005.
• 7: Kelly Quinn, Jessica Yang, and Vernon Turner. The next evolution in enterprise computing: The convergence of multicore x86 processing and 64-bit operating systems-white paper. Technical report, Advanced Micro Devices Inc., April 2005.
• 8: Jose Renau, Basilio Fraguela, James Tuck, Wei Liu, Milos Prvulovic, Luis Ceze, Smruti Sarangi, Paul Sack, Karin Strauss, and Pablo Montesinos. SESC simulator, January 2005. http://sesc.sourceforge.net.
• 9: David Brooks , Vivek Tiwari , Margaret Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, p.83-94, June 2000, Vancouver, British Columbia, Canada
• 10: Premkishore Shivakumar and Norman P. Jouppi. CACTI 3.0: An integrated cache timing, power, and area model. Technical Report 2001/2, Western Research Laboratory, Compaq, 2001.
• 11: Jaehyuk Huh , Doug Burger , Stephen W. Keckler, Exploring the Design Space of Future CMPs, Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques, p.199-210, September 08-12, 2001
• 12: M. Ekman and P. Stenstrom. Performance and power impact of issue-width in chip-multiprocessor cores. In ICPP'03: Proceedings of the 2003 International Conference on Parallel Processing, pages 359--369, Washington, DC, USA, 2003. IEEE Computer Society.
• 13: Stefanos Kaxiras , Girija Narlikar , Alan D. Berenbaum , Zhigang Hu, Comparing power consumption of an SMT and a CMP DSP for mobile phone workloads, Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems, November 16-17, 2001, Atlanta, Georgia, USA [doi>10.1145/502217.502254]
• 14: Ed Grochowski , Ronny Ronen , John Shen , Hong Wang, Best of Both Latency and Throughput, Proceedings of the IEEE International Conference on Computer Design (ICCD'04), p.236-243, October 11-13, 2004
• 15: J. Li and J. F. Martinez. Power-performance implications of thread-level parallelism on chip multiprocessors. In ISPASS'05: Proceedings of the 2005 International Symposium on Performance Analysis of Systems and Software, pages 124--134, Washington, DC, USA, 2005. IEEE Computer Society.
• 16: J. Li and J. F. Martinez. Dynamic power-performance adaptation of parallel computation on chip multiprocessors. In HPCA '06: Proceedings of the 12th International Symposium on High Performance Computer Architecture, Washington, DC, USA, 2006. IEEE Computer Society.
• 17: Yingmin Li , David Brooks , Zhigang Hu , Kevin Skadron, Performance, Energy, and Thermal Considerations for SMT and CMP Architectures, Proceedings of the 11th International Symposium on High-Performance Computer Architecture, p.71-82, February 12-16, 2005 [doi>10.1109/HPCA.2005.25]
• 18: Y. Li, B. Lee, D. Brooks, Z. Hu, and K. Skadron. CMP design space exploration subject to physical constraints. In HPCA '06: Proceedings of the 12th International Symposium on High Performance Computer Architecture, Washington, DC, USA, 2006. IEEE Computer Society.
• 19: Rakesh Kumar , Victor Zyuban , Dean M. Tullsen, Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling, Proceedings of the 32nd Annual International Symposium on Computer Architecture, p.408-419, June 04-08, 2005
• 20: K. Sankaranarayanan, S. Velusamy, M. Stan, and K. Skadron. A case for thermal-aware floorplanning at the microarchitectural level. Journal of Instruction Level Parallelism, 2005.
• 21: Pedro Chaparro , Grigorios Magklis , Jose Gonzalez , Antonio Gonzalez, Distributing the Frontend for Temperature Reduction, Proceedings of the 11th International Symposium on High-Performance Computer Architecture, p.61-70, February 12-16, 2005 [doi>10.1109/HPCA.2005.12]
• 22: Ja Chun Ku , Serkan Ozdemir , Gokhan Memik , Yehea Ismail, Thermal Management of On-Chip Caches Through Power Density Minimization, Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, p.283-293, November 12-16, 2005, Barcelona, Spain [doi>10.1109/MICRO.2005.36]
• 23: V. Zyuban , P. N. Strenski, Balancing hardware intensity in microprocessor pipelines, IBM Journal of Research and Development, v.47 n.5-6, p.585-598, September 2003
• 24: R. E. Kessler, The Alpha 21264 Microprocessor, IEEE Micro, v.19 n.2, p.24-36, March 1999 [doi>10.1109/40.755465]
• 25: Subbarao Palacharla , Norman P. Jouppi , J. E. Smith, Complexity-effective superscalar processors, Proceedings of the 24th annual international symposium on Computer architecture, p.206-218, June 01-04, 1997, Denver, Colorado, United States
• 26: Hang-Sheng Wang , Xinping Zhu , Li-Shiuan Peh , Sharad Malik, Orion: a power-performance simulator for interconnection networks, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
• 27: Weiping Liao, Lei He, and K. M. Lepak. Temperature and supply Voltage aware performance and power modeling at microarchitecture level. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(7):1042.
• 28: Steven Cameron Woo , Moriyoshi Ohara , Evan Torrie , Jaswinder Pal Singh , Anoop Gupta, The SPLASH-2 programs: characterization and methodological considerations, Proceedings of the 22nd annual international symposium on Computer architecture, p.24-36, June 22-24, 1995, S. Margherita Ligure, Italy
• 29: Man-Lap Li, Ruchira Sasanka, Sarita V. Adve, Yen-Kuang Chen, and Eric Debes. The alpbench benchmark suite for complex multimedia applications. In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC-2005), Washington, DC, USA, 2005. IEEE Computer Society.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Multiple-instruction-stream, multiple-data-stream processors (MIMD)

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.4 Parallel Architectures
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Performance attributes; Design studies

General Terms:
Design, Performance