A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems

ABSTRACT

The working set size of Java applications on embedded systems has recently been increasing, causing the Translation Lookaside Buffer (TLB) to become a serious performance bottleneck. From a thorough analysis of the SPECjvm98 benchmark suite executing on a commodity embedded system, we find TLB misses attribute from 24% to 50% of the total execution time. We explore and evaluate a wide spectrum of TLB-enhancing techniques with different combinations of software/hardware approaches, namely superpage for reducing TLB miss rates, two-level TLB and TLB prefetching for reducing both TLB miss rates and TLB miss latency, and even a no-TLB design for removing TLB overhead completely. We adapt and then in a novel way extend these approaches to fit the design space of embedded systems executing Java code. We compare these approaches, discussing their performance behavior, software/hardware complexity and constraints, especially the design implications for the application, runtime and OS.We first conclude that even with the aggressive approaches presented, there remains a performance bottleneck with the TLB. Second, in addition to facing very different design considerations and constraints for embedded systems, proven hardware techniques, such as TLB prefetching have different performance implications. Third, software based solutions, no-TLB design and superpaging, appear to be more effective in improving Java application performance on embedded systems. Finally, beyond performance, these approaches have their respective pros and cons; it is left to the system designer to make the appropriate engineering tradeoff.

REFERENCES

• 1: Ashley Saulsbury , Fredrik Dahlgren , Per Stenström, Recency-based TLB preloading, Proceedings of the 27th annual international symposium on Computer architecture, p.117-127, June 2000, Vancouver, British Columbia, Canada
• 2: Doug Joseph , Dirk Grunwald, Prefetching Using Markov Predictors, IEEE Transactions on Computers, v.48 n.2, p.121-133, February 1999 [doi>10.1109/12.752653]
• 3: Gansha Wu, Xin Zhou, Biao Chen, Peng Guo, Jinzhan Peng, Victor Ying. Memory Management for Multitasking Java on Resource-Constrained Devices. Submitted to HiPEAC'07.
• 4: Gansha Wu, Xin Zhou, Guei-Yuan Lueh, Jesse Z. Fang, Peng Guo, Jinzhan Peng, Victor Ying. XAMM: A High-performance Automatic Memory Management System with Memory-Constrained Designs. In the proceeding of HiPEAC 2005:130--149
• 5: Gokul B. Kandiraju , Anand Sivasubramaniam, Characterizing the d-TLB behavior of SPEC CPU2000 benchmarks, Proceedings of the 2002 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, June 15-19, 2002, Marina Del Rey, California
• 6: Gokul B. Kandiraju , Anand Sivasubramaniam, Going the distance for TLB prefetching: an application-driven study, Proceedings of the 29th annual international symposium on Computer architecture, p.195, May 25-29, 2002, Anchorage, Alaska
• 7: J. Bradley Chen , Anita Borg , Norman P. Jouppi, A simulation based study of TLB performance, Proceedings of the 19th annual international symposium on Computer architecture, p.114-123, May 19-21, 1992, Queensland, Australia
• 8: Juan Navarro , Sitaram Iyer , Peter Druschel , Alan Cox, Practical, transparent operating system support for superpages, Proceedings of the 5th symposium on Operating systems design and implementation

  Due to copyright restrictions we are not able to make the PDFs for this conference available for downloading

  , December 09-11, 2002, Boston, Massachusetts [doi>10.1145/1060289.1060299]
• 9: Madhusudhan Talluri , Mark D. Hill, Surpassing the TLB performance of superpages with less operating system support, Proceedings of the sixth international conference on Architectural support for programming languages and operating systems, p.171-182, October 05-07, 1994, San Jose, California, United States
• 10: Mark Aiken, Mänuel Fahndrich, Chris Hawblitzel Galen C. Hunt, and James R. Larus. Deconstructing Process Isolation. Microsoft Research Technical Report MSR-TR-2006-43. Microsoft Corporation, Redmond, WA, April 2006.
• 11: N. Ganapathy and C. Schimmei. General purpose operating system support for multiple page sizes. In Proceedings of the USENIX 1998.
• 12: S. J. Winwood, Y. Shuf, and H. Franke. Multiple page size support in the Linux kernel. In Proceedings of Ottawa Linux Symposium, Ottawa, Canada, June 2002.
• 13: Jean-Loup Baer , Tien-Fu Chen, Effective Hardware-Based Data Prefetching for High-Performance Processors, IEEE Transactions on Computers, v.44 n.5, p.609-623, May 1995 [doi>10.1109/12.381947]
• 14: Zhen Fang , Lixin Zhang , John B. Carter , Wilson C. Hsieh , Sally A. McKee, Reevaluating Online Superpage Promotion with Hardware Support, Proceedings of the 7th International Symposium on High-Performance Computer Architecture, p.63, January 20-24, 2001
• 15: Zhen Fang and Lixin Zhang. A Comparison of Online Superpage Promotion Mechanisms. www2.cs.utah.edu/impulse/papers/UUCS-99-021.ps.gz
• 16: SpecJVM98, http://www.spec.org/jvm98/
• 17: Yefim Shuf , Mauricio J. Serrano , Manish Gupta , Jaswinder Pal Singh, Characterizing the memory behavior of Java workloads: a structured view and opportunities for optimizations, ACM SIGMETRICS Performance Evaluation Review, v.29 n.1, p.194-205, June 2001

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS

General Terms:
Design, Experimentation, Measurement, Performance

Keywords:
Java, TLB performance, embedded system