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Mitigating soft error failures for multimedia applications by selective data protection
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Source International Conference on Compilers, Architecture and Synthesis for Embedded Systems archive
Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems table of contents
Seoul, Korea
SESSION: Robustness table of contents
Pages: 411 - 420  
Year of Publication: 2006
ISBN:1-59593-543-6
Authors
Kyoungwoo Lee  University of California, Irvine, CA
Aviral Shrivastava  Arizona State University, Tempe, AZ
Ilya Issenin  University of California, Irvine, CA
Nikil Dutt  University of California, Irvine, CA
Nalini Venkatasubramanian  University of California, Irvine, CA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
ACM  New York, NY, USA
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ABSTRACT

With advances in process technology, soft errors(SE)are becoming an increasingly critical design concern. Due to their large area and high density, caches are worst hit by soft errors. Although Error Correction Code based mechanisms protect the data in caches, they have high performance and power overheads. Since multimedia applications are increasingly being used in mission-critical embedded systems where both reliability and energy are a major concern, there is a de?nite need to improve reliability in embedded systems, without too much energy overhead. We observe that while a soft error in multimedia data may only result in a minor loss in QoS, a soft error in avariable that controls the execution ?ow of the program may be fatal. Consequently, we propose to partition the data space into failure critical and failure non-critical data, and provide a high-degree of soft error protection only to the failure critical data in Horizontally Partitioned Caches. Experimental results demonstrate that our selective data protection can achieve the failure rate close to that of a soft error protected cache system, while retaining the performance and energy consumption similar to those of a traditional cache system, with some degradation in QoS. For example, for conventional con?guration as in IntelXScale, our approach achieves the same failure rate, while improving performance by 28% and reducing energy consumption by 29%in comparison with a soft error protected cache.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Kyoungwoo Lee: colleagues
Aviral Shrivastava: colleagues
Ilya Issenin: colleagues
Nikil Dutt: colleagues
Nalini Venkatasubramanian: colleagues