FlashCache: a NAND flash memory file cache for low power web servers

ABSTRACT

We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a relatively small DRAM, which includes a primary file buffer cache, and a flash memory secondary file buffer cache. Compared to a conventional DRAM-only architecture, our architecture consumes orders of magnitude less idle power while remaining cost effective. This is a result of using flash memory, which consumes orders of magnitude less idle power than DRAM and is twice as dense. The client request behavior in web servers, allows us to show that the primary drawbacks of flash memory?endurance and long write latencies?can easily be overcome. In fact the wear-level aware management techniques that we propose are not heavily used.

REFERENCES

• 1: Error Correction Code in Single Level Cell NAND Flash Memories. http://www. st. com/stonline/products/literature/an/10123. pdf.
• 2: Hybrid Hard Drives with Non-Volatile Flash and Longhorn. http://www. samsung. com/Products/HardDiskDrive/news/HardDiskDrive_20050425_0000117556. htm.
• 3: JFFS:The Journalling Flash File System. http://sources. redhat. com/jffs2/jffs2. pdf.
• 4: Micron DDR2 DRAM. http://www. micron. com/products/dram/ddr2/.
• 5: The Micron system-power calculator. http://www. micron. com/products/dram/syscalc. html.
• 6: Samsung NAND Flash memory datasheet. http://www. samsung. com/products/semiconductor/NANDFlash/SLC_LargeBlock/8Gbit/K9K8G08U0A/K9K8G08U0A. htm.
• 7: SPECweb99 benchmark. http://www. spec. org/osg/web99/.
• 8: Sun Fire T2000 Server Power Calculator. http://www. sun. com/servers/coolthreads/t2000/calc/index. jsp.
• 9: TrueFFS. http://www. m-systems. com/site/en-US/Support/DeveloperZone/Software/LifespanCalc. htm.
• 10: ITRS roadmap. Technical report, 2005.
• 11: Paul Barford , Mark Crovella, Generating representative Web workloads for network and server performance evaluation, Proceedings of the 1998 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems, p.151-160, June 22-26, 1998, Madison, Wisconsin, United States
• 12: Nathan L. Binkert , Ronald G. Dreslinski , Lisa R. Hsu , Kevin T. Lim , Ali G. Saidi , Steven K. Reinhardt, The M5 Simulator: Modeling Networked Systems, IEEE Micro, v.26 n.4, p.52-60, July 2006 [doi>10.1109/MM.2006.82]
• 13: E. L. Congduc. Packet classi cation in the NIC for improved SMP-based internet servers. In Proc. Int 'l Conf. on Networking, Feb. 2004.
• 14: Magnus Ekman , Per Stenstrom, A Cost-Effective Main Memory Organization for Future Servers, Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers, p.45.1, April 04-08, 2005 [doi>10.1109/IPDPS.2005.12]
• 15: S. Gregori, A. Cabrini, O. Khouri, and G. Torelli. On-chip error correcting techniques for new-generation flash memories. 91(4), Apr 2003.
• 16: S. Gupta, M. Hilbert, S. Hong, and R. Patti. Techniques for producing 3D ICs with high-density interconnect. www. tezzaron. com/about/papers/ieee_vmic_2004_finalsecure. pdf.
• 17: H. Huang, P. Pillai, and K. G. Shin. Design and Implementation of Power-Aware Virtual Memory. In USENIX Annual Technical Conference, pages 57--70, 2003.
• 18: Poonacha Kongetira , Kathirgamar Aingaran , Kunle Olukotun, Niagara: A 32-Way Multithreaded Sparc Processor, IEEE Micro, v.25 n.2, p.21-29, March 2005 [doi>10.1109/MM.2005.35]
• 19: Alvin R. Lebeck , Xiaobo Fan , Heng Zeng , Carla Ellis, Power aware page allocation, Proceedings of the ninth international conference on Architectural support for programming languages and operating systems, p.105-116, November 2000, Cambridge, Massachusetts, United States
• 20: J. Lee, S.-S. Lee, O.-S. Kwon, K.-H. Lee, D.-S. Byeon, I. -Y. Kim, K.-H. Lee, Y.-H. Lim, B.-S. Choi, J.-S. Lee, W.-C. Shin, J.-H. Choi, and K.-D. Suh. A 90-nm CMOS 1. 8-V 2-Gb NAND Flash Memory for Mass Storage Applications. 38(11), Nov 2003.
• 21: G. MacGillivray. Process vs. density in DRAMs. http://www. eetasia. com/ARTICLES/2005SEP/B/2005SEP01_STOR_TA. pdf.
• 22: Chanik Park , Jaeyu Seo , Sunghwan Bae , Hyojun Kim , Shinhan Kim , Bumsoo Kim, A low-cost memory architecture with NAND XIP for mobile embedded systems, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, October 01-03, 2003, Newport Beach, CA, USA [doi>10.1145/944645.944684]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.1 Semiconductor Memories

Additional Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: System architectures

General Terms:
Design, Experimentation, Performance

Keywords:
application-specific architectures, embedded system, flash memory, full-system, low power, server platforms, simulation, web server