Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications

ABSTRACT

The memory subsystem of a complex multiprocessor systems-on-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as of communication architecture, both affect the power efficiency of the design. In this paper we propose a novel approach that enables energy-aware co-synthesis of both memory and communication architecture for streaming applications. As opposed to earlier techniques, we employ a powerful compile-time analysis of memory access behavior that adds flexibility in selecting memory architectures. Additionally, we target TDMA bus-based communication architectures, which not only guarantee performance, but also greatly reduce the design time and allow us to find the energy optimal system configuration. We propose and compare three techniques: an optimal mixed ILP-based co-synthesis technique, a mixed ILP-based traditional two-step synthesis approach where memory and communication synthesis is performed sequentially, and a co-synthesis heuristic that synthesizes energy-efficient hierarchical bus-based communication architectures with guaranteed throughput. Our experimental results on a number of streaming applications show that both the traditional two-step synthesis approach and heuristic result in up to 50% worse power consumption in comparison with proposed co-synthesis approach. However, on some of the streaming benchmarks, our co-synthesis heuristic approach was able to find optimal or near-optimal results in a much shorter time than the MILP co-synthesis approach.

REFERENCES

• 1: Yazdan Aghaghiri , Farzan Fallah , Massoud Pedram, Irredundant address bus encoding for low power, Proceedings of the 2001 international symposium on Low power electronics and design, p.182-187, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383128]
• 2: K. Banerjee, A. Mehrotra. A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs. IEEE Trans. on Electron Devices, vol. 49, no. 11, Nov 2002.
• 3: D. Burger and T. Austin. The SimpleScalar tool set, version 2.0. TR 1342, University of Wisconsin-Madison, CS Dept., 1997.
• 4: Lukai Cai , Haobo Yu , Daniel Gajski, A novel memory size model for variable-mapping in system level design, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.812-817, January 27-30, 2004, Yokohama, Japan
• 5: J. Y. Chen , W. B. Jone , J. S. Wang , H.-I. Lu , T. F. Chen, Segmented bus design for low-power systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.1, p.25-29, March 1999 [doi>10.1109/92.748197]
• 6: CPLEX ILP solver, www.cplex.com.
• 7: Michael Gasteier , Manfred Glesner, Bus-based communication synthesis on system level, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.1, p.1-11, Jan. 1999 [doi>10.1145/298865.298866]
• 8: Ilya Issenin , Erik Brockmeyer , Bart Durinck , Nikil Dutt, Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1146925]
• 9: Sungchan Kim , Chaeseok Im , Soonhoi Ha, Efficient exploration of on-chip bus architectures and memory allocation, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden [doi>10.1145/1016720.1016779]
• 10: Damien Lyonnard , Sungjoo Yoo , Amer Baghdadi , Ahmed A. Jerraya, Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip, Proceedings of the 38th conference on Design automation, p.518-523, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379015]
• 11: MPARM project, http://www-micrel.deis.unibo.it/sitonew/research/mparm.html
• 12: Sudeep Pasricha , Nikil Dutt, COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
• 13: Sudeep Pasricha , Nikil Dutt , Mohamed Ben-Romdhane, Automated throughput-driven synthesis of bus-based communication architectures, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China [doi>10.1145/1120725.1120920]
• 14: Alessandro Pinto , Luca P. Carloni , Alberto L. Sangiovanni-Vincentelli, Constraint-driven communication synthesis, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514114]
• 15: Kyeong Keol Ryu , Vincent J. Mooney III, Automated Bus Generation for Multiprocessor SoC Design, Proceedings of the conference on Design, Automation and Test in Europe, p.10282, March 03-07, 2003
• 16: Sonics Inc. http://www.sonicsinc.com/sonics/products/siliconbackplaneIII/
• 17: P. Stobach. A new technique in scene adaptive coding. In Proc. of EUSIPCO, Grenoble, 1988.
• 18: Hua Wang , Antonis Papanikolaou , Miguel Miranda , Francky Catthoor, A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.759-761, January 27-30, 2004, Yokohama, Japan
• 19: P. Wolkotte et al. Energy-Efficient NoC for Best-Effort Communication. ICFPLA, 2005.
• 20: Hui Zhang , Jan Rabaey, Low-swing interconnect interface circuits, Proceedings of the 1998 international symposium on Low power electronics and design, p.161-166, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280876]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS

General Terms:
Algorithms, Design, Performance

Keywords:
communication synthesis, customized memory hierarchy, data reuse, hierarchical TDMA buses, multiprocessor system-on-chip