Generic netlist representation for system and PE level design exploration

ABSTRACT

Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems require more productive design approaches starting from high-level languages such as C. On the other hand, tight constraints of embedded systems require careful design exploration at system level (coarse grained exploration) and at the processing-element (PE) level (fine grained exploration).In this paper we presented GNR, a formal modeling approach, developed to improve productivity of designing systems and processing elements, the same way that traditional ADLs improved productivity for designing processors. The GNR is an order of magnitude shorter than state-of-the-art ADLs with RTL generation capabilities and yet can capture any structural details that affect the implementation quality. Using relatively short GNR description, we explored several designs for implementing an MP3 decoder and achieved 3.25 speedup compared to MicroBlaze processor. We have also developed a web-based interface for our tools, so that users can upload and evaluate new architectures described in GNR. Our toolset and GNR is an intermediate step towards synthesis of TLM to RTL.

REFERENCES

• 1: P. Mishra and N. Dutt, "Architecture Description Languages for Programmable Embedded Systems", IEE Proc. on Computers and Digital Techniques (CDT), Special issue on Embedded Microelectronic Systems: Status and Trends, vol. 152, no 3, 2005.
• 2: W. Qin and S. Malik, "Architecture Description Languages for Retargetable Compilation", in The Compiler Design Handbook: Optimizations & Machine Code Generation. Y. N. Srikant and Priti Shankar, CRC Press, 2002.
• 3: A. Hoffmann, T. Kogel, A. Nohl, G. Braun, O. Schliebusch, A. Wieferink, and H. Meyr. A Novel Methodology for the Design of Application Specific Instruction Set Processors (ASIP) Using a Machine Description Language. IEEE Transactions on Computer-Aided Design, 20(11):1338--1354, Nov. 2001.
• 4: Prabhat Mishra , Arun Kejariwal , Nikil Dutt, Synthesis-driven Exploration of Pipelined Embedded Processors, Proceedings of the 17th International Conference on VLSI Design, p.921, January 05-09, 2004
• 5: H. Akaboshi, "A Study on Design Support for Computer Architecture Design", Doctoral Thesis, Depart. of Information Systems, Kyushu Univ., Japan, Jan. 1996
• 6: R. Leupers and P. Marwedel, "Retargetable Code Generation based on Structural Processor Descriptions," Design Automation for Embedded Systems, vol. 3, no. 1, 1998.
• 7: Rainer Leupers , Peter Marwedel, Retargetable Generation of Code Selectors from HDL Processor Models, Proceedings of the 1997 European conference on Design and Test, p.140, March 17-20, 1997
• 8: A. Chattopadhyay, D. Kammler, E. Witte, O. Schliebusch, H. Ishebabi, B. Geukes, R. Leupers, G. Ascheid, "Automatic Low Power Optimizations during ADL-driven ASIP Design", VLSI-DAT, 2006.
• 9: Mehrdad Reshadi , Daniel Gajski, A cycle-accurate compilation algorithm for custom pipelined datapaths, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA [doi>10.1145/1084834.1084845]
• 10: B. Gorjiara, D. Gajski, "Custom Processor Design Using NISC: A Case-Study on DCT algorithm", ESTIMEDIA, 2005.
• 11: http://www.cecs.uci.edu/~nisc
• 12: XML: http://www.w3.org/XML/
• 13: XML Schema: http://www.w3.org/XML/Schema
• 14: http://www.underbit.com/products/mad/
• 15: Hansu Cho , Samar Abdi , Daniel Gajski, Design and implementation of transducer for ARM-TMS communication, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan [doi>10.1145/1118299.1118339]
• 16: B. Gorjiara, M. Reshadi, D. Gajski, "NISC Communication Interface", Center for Embedded Computer Systems (CECS) Technical Report TR 06-05, 2006.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Automatic synthesis

Additional Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Systems specification methodology; Modeling of computer architecture

General Terms:
Design, Languages, Performance

Keywords:
GNR, NISC, application-specific processor, architecture description language, modeling, synthesis, system design