Yield prediction for architecture exploration in nanometer technology nodes:: a model and case study for memory organizations

ABSTRACT

Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing violations. Conventional yield models do not allow to accurately analyze this, at least not at the system level. In this paper we propose a technique to estimate this system level yield loss for a number of alternative memory organization implementations. This can aid the designer into making educated trade-offs at the architecture level between energy consumption and parametric timing yield by using memories from different available libraries with different energy/performance characteristics considering the impact of manufacturing variations. The accuracy of this technique is very high, an average error of less than 1% is reported, which enables an early exploration of the available options.

REFERENCES

• 1: Ashish Srivastava , Dennis Sylvester , David Blaauw, Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design, Proceedings of the conference on Design, automation and test in Europe, p.10718, February 16-20, 2004
• 2: Todd Austin , David Blaauw , Trevor Mudge , Krisztián Flautner, Making Typical Silicon Matter with Razor, Computer, v.37 n.3, p.57-65, March 2004 [doi>10.1109/MC.2004.1274005]
• 3: Shekhar Borkar, Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation, IEEE Micro, v.25 n.6, p.10-16, November 2005 [doi>10.1109/MM.2005.110]
• 4: Chandu Visweswariah, Death, taxes and failing chips, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775921]
• 5: A. Papanikolaou , F. Lobmaier , H. Wang , M. Miranda , F. Catthoor, A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA [doi>10.1145/1084834.1084866]
• 6: Puneet Gupta , Andrew B. Kahng, Manufacturing-Aware Physical Design, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.681, November 09-13, 2003 [doi>10.1109/ICCAD.2003.94]
• 7: A. Papoulis, "The Fourier integral and its applications", McGraw-Hill, 1962.
• 8: C. Genest, A.C. Favre, "Everything you always wanted to know about copula modeling but were afraid to ask",Journal of Hydrologic Engineering, 11, 2006
• 9: Y. Cao et al, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design", CICC, 2000.
• 10: Ashish Srivastava , Saumil Shah , Kanak Agarwal , Dennis Sylvester , David Blaauw , Stephen Director, Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA [doi>10.1145/1065579.1065718]
• 11: Ashish Srivastava , Dennis Sylvester , David Blaauw, Statistical optimization of leakage power considering process variations using dual-Vth and sizing, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996775]
• 12: Murari Mani , Anirudh Devgan , Michael Orshansky, An efficient algorithm for statistical minimization of total power under timing yield constraints, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA [doi>10.1145/1065579.1065661]
• 13: International Technology Roadmap for Semiconductors, 2005 edition, http://public.itrs.net
• 14: H. Wang et al., "Variable Tapered Pareto Buffer Design and Implementation Techniques Allowing Run-Time Configuration for Low Power Embedded SRAMs", IEEE Trans. on VLSI, Oct. 2005
• 15: H.Wang et al., "Impact of deep submicron (DSM) process variation effects in SRAM design", DATE, 2005.
• 16: A. Agarwal et al., "Process variation in embedded memories: failure analysis and variation aware architecture" IEEE Journal of Solid-State Circuits, Sept. 2005.
• 17: C. Visweswariah, "Statistical Timing of Digital Integrated Circuits", Microprocessor Circuit Design Forum at ISSCC 2004.
• 18: Francky Catthoor , Eddy de Greef , Sven Suytack, Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design, Kluwer Academic Publishers, Norwell, MA, 1998
• 19: Jie Yang , Luigi Capodieci , Dennis Sylvester, Advanced timing analysis based on post-OPC extraction of critical dimensions, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA [doi>10.1145/1065579.1065676]
• 20: PDF Solutions Inc. http://www.pdf.com/
• 21: Kimish Patel , Enrico Macii , Massimo Poncino, Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC, Proceedings of the conference on Design, automation and test in Europe, p.10700, February 16-20, 2004
• 22: Artisan Memories http://www.artisan.com/
• 23: Virage Logic http://www.viragelogic.com/
• 24: Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000 [doi>10.1145/335043.335044]
• 25: Mathematica http://www.wolfram.com/

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Design, Performance, Reliability

Keywords:
parametric yield, process variability, system exploration