Creation and utilization of a virtual platform for embedded software optimization:: an industrial case study

ABSTRACT

Virtual platform (ViP), or ESL (Electronic System Level) simulation model, is one of the most widely renowned system level design techniques. In this paper, we present a case study of creating and applying the ViP in the development of a new hard disk system called Hybrid-HDD that is one of the main features in the Windows VISTA (R). First, we summarize how we developed the ViP including the levels of timing accuracy of models, automatic generation of models from RTL code, external subsystem models, etc. Then, we explain how we exploited the ViP in software optimization. Compared with the conventional flow of software development, e.g. based on the real board, the ViP gives a better profiling capability thereby allowing designers to find more chances of code optimization. Based on the simulation and analysis with the ViP, the software optimization could improve system performance by more than 50%. However, in our case study, we found that the current ViP technique needs further improvements to become a true ESL design technique.

REFERENCES

• 1: "System-Level IC Design Accelerates SoC Delivery", Nikkei Electronics ASIA, Feb. 2005.
• 2: SystemC White Paper, http://www.systemc.org
• 3: A. Haverinen, et al., "SystemC based SoC Communication Modeling for the OCP protocol", http://www.ocpip.org/, Oct. 2002.
• 4: ARM-ESL SocDesigner, http://www.arm.com
• 5: ConvergenSC, http://www.coware.com
• 6: Magillem, http://www.prosilo.com/products/magillem
• 7: Cocentric System Studio, http://www.synopsys.com/products/ cocentric_studio
• 8: J. A. Colgan, et al., Advancing Transaction Level Modeling (TLM): Linking the OSCI and OCP-IP Worlds at Transaction Level, http://www.opensystems-publishing.com/whitepapers
• 9: Real Time System Model, http://www.arm.com/products/DevTools/RealTimeSystem Model1176.html
• 10: Platform development kits, http://www.virtio.com
• 11: CoFluent Studio, http://www.cofluentdesign.com
• 12: Kurt Keutzer, Hardware/software co-simulation, Proceedings of the 31st annual conference on Design automation, p.439-440, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196458]
• 13: R. Klein, Miami: a hardware software co-simulation environment, Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96), p.173, June 19-21, 1996
• 14: Achim Nohl , Gunnar Braun , Oliver Schliebusch , Rainer Leupers , Heinrich Meyr , Andreas Hoffmann, A universal technique for fast and flexible instruction-set architecture simulation, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.513927]
• 15: Sungjoo Yoo , Iuliana Bacivarov , Aimen Bouchhima , Yanick Paviot , Ahmed A. Jerraya, Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer, Proceedings of the conference on Design, Automation and Test in Europe, p.10550, March 03-07, 2003
• 16: Luc Séméria , Abhijit Ghosh, Methodology for hardware/software co-verification in C/C++ (short paper), Proceedings of the 2000 conference on Asia South Pacific design automation, p.405-408, January 2000, Yokohama, Japan [doi>10.1145/368434.368712]
• 17: M. Bradley, K. Xie, "Hardware/Software Co-Verification with RTOS Application Code", http://www.techonline.com/community/tech_tipic/21082
• 18: M. AbdElSalam Hassan , Keishi Sakanushi , Yoshinori Takeuchi , Masaharu Imai, RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC, Proceedings of the conference on Design, Automation and Test in Europe, p.554-559, March 07-11, 2005 [doi>10.1109/DATE.2005.263]
• 19: R. Siegmund , D. Müller, SystemCSV - an extension of SystemC for mixed multi-level communication modeling and interface-based system design, Proceedings of the conference on Design, automation and test in Europe, p.26-33, March 2001, Munich, Germany
• 20: Microsoft, WinHEC 2005 Conference Tracks, http://www.microsoft.com
• 21: Samsung, OneNAND product information, http://www.samsung.com
• 22: Tenison, vtoc product information, http://www.tenison.com
• 23: Hye-On Jang , Minsoo Kang , Myeong-jin Lee , Kwanyeob Chae , Kookpyo Lee , Kyuhyun Shim, High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study, Proceedings of the conference on Design, automation and test in Europe, p.10538, February 16-20, 2004
• 24: Silvia Brini , Doha Benjelloun , Fabien Castanier, A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL Modems, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20164, March 03-07, 2003
• 25: George Hadjiyiannis , Pietro Russo , Srinivas Devadas, A methodology for accurate performance evaluation in architecture exploration, Proceedings of the 36th ACM/IEEE conference on Design automation, p.927-932, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310100]
• 26: Sudeep Pasricha , Mohamed Ben-Romdhane, Using TLM for Exploring Bus-based SoC Communication Architectures, Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), p.79-85, July 23-25, 2005
• 27: MMAV, http://www.denali.com/products_mmav.html
• 28: Carbon, http://www.carbondesigns.com
• 29: Virtual Platform Designer, http://www.coware.com

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Design, Performance

Keywords:
embedded software optimization, hybrid HDD (hard disk drive), virtual platform (ViP)