Heterogeneous multiprocessor implementations for JPEG:: a case study

ABSTRACT

Heteregenous multiprocessor SoCs are becoming a reality, largely due to the abundance of transistors, intellectual property cores and powerful design tools. In this project, we explore the use of multiple cores to speed up the JPEG compression algorithm. We show two methods to parallelize this algorithm: one, a master-slave model; and two, a pipeline model. The systems were implemented using Tensilica's Xtensa LX processors with queues. We show that even with this relatively simple application, parallelization can be carried out with up to nine processors with utilization of between 50% to 80%. We obtained speed ups of up to 4.6X with a seven core system with an area increase of 3.1X.

REFERENCES

• 1: SystemC Initiative. (http://www.systemc.org).
• 2: Xtensa Processor. Tensilica Inc. (http://www.tensilica.com).
• 3: Flix: Fast relief for performance-hungry embedded applications. Tensilica Inc. (http://www.tensilica.com/pdf/FLIX_White_Paper_v2.pdf), 2005.
• 4: J. Axelsson. A Case Study in Heterogeneous Implementation of Automotive Real-Time Systems. In CODES'98, Seattle, 1998.
• 5: S. Banerjee, T. Hamada, P. M. Chau, and R. D. Fellman. Macro Pipelining Based Scheduling on High Performance Heterogeneous Multiprocessor Systems. Signal Processing, IEEE Transactions on, 43(6):1468--1484, 1995.
• 6: Task Partitioning Upon Heterogeneous Multiprocessor Platforms, Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'04), p.536, May 25-28, 2004
• 7: A. Berić, R. Sethuraman, C. A. Pinto, H. Peters, G. Veldman, P. van de Haar, and M. Duranton. Heterogeneous Multiprocessor for High Definition Video. In ICCE'06, pages 401--402, 2006.
• 8: Tracy D. Braun , Howard Jay Siegel , Anthony A. Maciejewski, Heterogeneous Computing: Goals, Methods, and Open Problems, Proceedings of the 8th International Conference on High Performance Computing, p.307-320, December 17-20, 2001
• 9: Karam S. Chatha , Ranga Vemuri, A tool for partitioning and pipelined scheduling of hardware-software systems, Proceedings of the 11th international symposium on System synthesis, p.145-151, December 02-04, 1998, Hsinchu, Taiwan, China
• 10: Sathish Gopalakrishnan , Marco Caccamo, Task Partitioning with Replication upon Heterogeneous Multiprocessor Systems, Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06), p.199-207, April 04-07, 2006 [doi>10.1109/RTAS.2006.43]
• 11: E. Hamilton. JPEG File Interchange Format. Technical report, C-Cube Microsystems, September 1 1992.
• 12: John L. Hennessy , David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 2003
• 13: J. Jeon and K. Choi. Loop Pipelining in Hardware-Software Partitioning. In ASP-DAC'98, pages 361--366, Yokohama, Japan, 1998.
• 14: M. Kim, D. Kim, and G. E. Sobelman. MPEG-4 performance analysis for a CDMA network-on-chip. In ICCCAS'05, pages 493--496, 2005.
• 15: Takeshi Kodaka , Keiji Kimura , Hironori Kasahara, Multigrain Parallel Processing for JPEG Encoding on a Single Chip Multiprocessor, Proceedings of the International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'02), p.57, January 10-11, 2002
• 16: Rakesh Kumar , Dean M. Tullsen , Norman P. Jouppi , Parthasarathy Ranganathan, Heterogeneous Chip Multiprocessors, Computer, v.38 n.11, p.32-38, November 2005 [doi>10.1109/MC.2005.379]
• 17: D. e. a. Pham. The design and implementation of a first-generation cell processor. In ISSCC 2005, pages 184--186. IEEE CS Press, 2005.
• 18: M. T. J. Strik, A. H. Timmer, J. L. van Meerbergen, and G.-J. van Rootselaar. Heterogeneous multiprocessor for the management of real-time video and graphics streams. Solid-State Circuits, IEEE Journal of, 35(11):1722--1731, 2000.
• 19: F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha. Custom-instruction synthesis for extensible-processor platforms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(2):216--228, 2004.
• 20: V. Živojnović, S. Pees, and H. Myer. LISA-machine description language and generic machine model for HW/SW co-design. In Workshop on VLSI Signal Processing, pages 127--136, 1996.
• 21: A. Wieferink, M. Doerper, R. Leupers, G. Ascheid, H. Meyr, T. Kogel, G. Braun, and A. Nohl. System Level Processor/Communication Co-exploration Methodology for Multiprocessor System-on-Chip Platforms. Computers and Digital Techniques, IEE Proceedings, 152(1):3--11, 2005.
• 22: N. Zhang and C.-H. Wu. Study on Adaptive Job Assignment for Multiprocessor Implementation of MPEG2 Video Encoding. Industrial Electronics, IEEE Transactions on, 44(5):726--734, 1997.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Design studies

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Heterogeneous (hybrid) systems

General Terms:
Design, Experimentation, Performance