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Pack instruction generation for media pUsing multi-valued decision diagram
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Source International Conference on Hardware Software Codesign archive
Proceedings of the 4th international conference on Hardware/software codesign and system synthesis table of contents
Seoul, Korea
SESSION: Application-specific code optimization table of contents
Pages: 154 - 159  
Year of Publication: 2006
ISBN:1-59593-370-0
Authors
Tanaka Hiroaki  Osaka University, Suita, Osaka, Japan
Yoshinori Takeuchi  Osaka University, Suita, Osaka, Japan
Keishi Sakanushi  Osaka University, Suita, Osaka, Japan
Masaharu Imai  Osaka University, Suita, Osaka, Japan
Yutaka Ota  Semiconductor Company, Toshiba Corporation, Saiwai-Ku, Kawasaki, Japan
Nobu Matsumoto  Semiconductor Company, Toshiba Corporation, Saiwai-Ku, Kawasaki, Japan
Masaki Nakagawa  Semiconductor Company, Toshiba Corporation, Saiwai-Ku, Kawasaki, Japan
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
ACM  New York, NY, USA
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ABSTRACT

SIMD instructions are often implemented in modern multimedia oriented processors. Although SIMD instructions are useful for many digital signal processing applications, most compilers do not exploit SIMD instructions. The difficulty in the utilization of SIMD instructions stems from data parallelism in registers. In assembly code generation, the positions of data in registers must be noted. A technique of generating pack instructions which pack or reorder data in registers is essential for exploitation of SIMD instructions. This paper presents a code generation technique for SIMD instructions with pack instructions. SIMD instructions are generated by finding and grouping the same operations in programs. After the SIMD instruction generation, pack instructions are generated. In the pack instruction generation, Multi-valued Decision Diagram (MDD) is introduced to represent and to manipulate sets of packed data. Experimental results show that our code generation technique can generate assembly code with SIMD and pack instructions performing complex repacking of 8 packed data in registers for a commercial VLIW processor with 6 pack instructions and achieved speedup ratio of up to 7.7.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Media embedded Processor, http://www.mepcore.com. 2005.
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S. M. Arvind Srinivasan Timothy Kam and R. K. Brayton. Algorithms for discrete function manipulation. In Proceedings of the IEEE International Conference on Computer-Aided Design, pages 92--95, November 1990.
 
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T. Miyamori, J. Tanabe, Y. Taniguchi, K. Furukawa, T. Kozakaya, H. Nakai, Y. Miyamoto, K. Maeda, and M. Matsui. Development of image recognition processor based on configurable processor. Journal of Robotics and Mechatronics, 17(4):437--446, 2005.

Collaborative Colleagues:
Tanaka Hiroaki: colleagues
Yoshinori Takeuchi: colleagues
Keishi Sakanushi: colleagues
Masaharu Imai: colleagues
Yutaka Ota: colleagues
Nobu Matsumoto: colleagues
Masaki Nakagawa: colleagues