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ABSTRACT
In this paper we propose a solution for a worst-case execution time (WCET) analyzable Java system: a combination of a time predictable Java processor and a tool that performs WCET analysis of Java bytecode. We present a Java processor, called JOP, designed for time-predictable execution of real-time tasks. JOP is an implementation of the Java virtual machine (JVM) in hardware. The execution time of bytecodes, the instructions of the JVM, is known cycle accurate for JOP. Therefore, JOP simplifies the low-level WCET analysis. A method cache, that fills whole Java methods into the cache, is analyzable with respect to the WCET. The WCET analysis tool is based on integer linear programming. The tool performs the low-level analysis at the bytecode level and integrates the method cache analysis for a two block cache.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
|
C. Artho and A. Biere. Subroutine inlining and bytecode abstraction to simplify static and dynamic analysis. Electronic Notes in Theoretical Computer Science, 141(1):109--128, December 2005.
|
| |
2
|
|
| |
3
|
G. Bernat, A. Burns, and A. Wellings. Portable worst-case execution time analysis using java byte code. In Proc. 12th EUROMICRO Conference on Real-time Systems, Jun 2000.
|
| |
4
|
|
| |
5
|
M. Dahm. Byte code engineering with the BCEL API. Technical report, Freie Universitat Berlin, April 2001.
|
| |
6
|
DCT. Lightfoot 32-bit Java processor core. data sheet, September 2001.
|
| |
7
|
Sujit Dey , Debashis Panigrahi , Li Chen , Clark N. Taylor , Krishna Sekar , Pablo Sanchez, Using a Soft Core in a SoC Design: Experiences with picoJava, IEEE Design & Test, v.17 n.3, p.60-71, July 2000
[doi> 10.1109/54.867896]
|
| |
8
|
|
| |
9
|
T. R. Halfhill. Imsys hedges bets on Java. Microprocessor Report, August 2000.
|
| |
10
|
|
| |
11
|
Imsys. Im1101c (the cjip) technical reference manual/v0.25, 2004.
|
| |
12
|
J. Kreuzinger, U. Brinkschulte, M. Pfeffer, S. Uhrig, and T. Ungerer. Real-time event-handling and scheduling on a multithreaded Java microcontroller. Microprocessors and Microsystems, 27(1):19--31, 2003.
|
 |
13
|
Yau-Tsun Steven Li , Sharad Malik, Performance analysis of embedded software using implicit path enumeration, Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems, p.88-98, November 1995, La Jolla, California, United States
|
| |
14
|
|
| |
15
|
|
| |
16
|
|
| |
17
|
|
| |
18
|
|
| |
19
|
|
| |
20
|
|
| |
21
|
|
| |
22
|
|
| |
23
|
M. Schoeberl. A time predictable instruction cache for a Java processor. In On the Move to Meaningful Internet Systems 2004: Workshop on Java Technologies for Real-Time and Embedded Systems (JTRES 2004), volume 3292 of LNCS, pages 371--382, Agia Napa, Cyprus, October 2004. Springer.
|
| |
24
|
M. Schoeberl. Evaluation of a Java processor. In Tagungsband Austrochip 2005, pages 127--134, Vienna, Austria, October 2005.
|
| |
25
|
M. Schoeberl. JOP: A Java Optimized Processor for Embedded Real-Time Systems. PhD thesis, Vienna University of Technology, 2005.
|
| |
26
|
|
| |
27
|
|
| |
28
|
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CITED BY 10
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Walter Binder , Alex Villazón , Martin Schoeberl , Philippe Moret, Cache-aware cross-profiling for java processors, Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, October 19-24, 2008, Atlanta, GA, USA
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|
|
|
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|
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Thomas Bøgholm , Henrik Kragh-Hansen , Petur Olsen , Bent Thomsen , Kim G. Larsen, Model-based schedulability analysis of safety critical hard real-time Java programs, Proceedings of the 6th international workshop on Java technologies for real-time and embedded systems, September 24-26, 2008, Santa Clara, California
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|
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