Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture

ABSTRACT

Coarse-grained reconfigurable architecture aims to achieve both performance and flexibility. However, power consumption is no less important for the reconfigurable architecture to be used as a competitive processing core in embedded systems. In this paper, we show how power is consumed in a typical coarse-grained reconfigurable architecture. Based on the power breakdown data, we suggest a power-conscious configuration cache structure and code mapping technique, which reduce power consumption without performance degradation. Experimental results show that the proposed approach saves much power even with reduced configuration cache size.

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Adaptable architectures

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Pipeline processors; Heterogeneous (hybrid) systems

General Terms:
Design, Experimentation, Performance, Verification

Keywords:
coarse-grained reconfigurable architecture (CGRA), configuration cache, context pipelining, loop pipelining, low power, spatial mapping, system-on-chip (SoC), temporal mapping