| Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation |
| Full text |
Pdf
(215 KB)
|
| Source
|
International Symposium on Low Power Electronics and Design
archive
Proceedings of the 2006 international symposium on Low power electronics and design
table of contents
Tegernsee, Bavaria, Germany
SESSION: Leakage control and dynamic power optimization
table of contents
Pages: 220 - 225
Year of Publication: 2006
ISBN:1-59593-462-6
|
|
Authors
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 2, Downloads (12 Months): 46, Citation Count: 2
|
|
|
ABSTRACT
In this work we present a SPICE-based RTL subthreshold-leakage model analyzing components built in 70nm technology [1]. We present a separation approach regarding inter- and intra-die threshold variations, temperature, supply-voltage, and state dependence. The body-effect and differences between NMOS and PMOS introduce a leakage state dependence of one order of magnitude[2, 3]. We show that the leakage of RT-components still shows state dependencies between 20% and $80%. A leakage model not regarding the state can never be more accurate than this. The proposed state aware model has an average error of 6.7% for the RT-components analyzed.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Berkeley Predictive Technology Model: www-device.eecs.berkeley.edu/~ptm/
|
 |
2
|
|
 |
3
|
Ashish Srivastava , Robert Bai , David Blaauw , Dennis Sylvester, Modeling and analysis of leakage power considering within-die process variations, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
[doi> 10.1145/566408.566426]
|
| |
4
|
K Roy, S Mukhopadhyay, H Mahmoodi-Meimand: Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits. Proc. of the IEEE Vol.91 No.2, 2003.
|
| |
5
|
C Hu: BSIM Model for Circuit Design Using Advanced Technologies. 2001 Symposium on VLSI Circuit Digest of Technical Papers, 2001.
|
 |
6
|
|
 |
7
|
|
| |
8
|
D Helms, E Schmidt, W Nebel: Leakage in CMOS circuits - An Introduction. PATMOS, 2004.
|
| |
9
|
D Lee D Blaauw, D Sylvester: Static Leakage Reduction Through Simultaneous V_T/T_ox and State Assignment. IEEE Tran on CAD of ICs and Systems Vol24 No7, 2004
|
 |
10
|
|
| |
11
|
D Helms, M Hoyer, W Nebel: Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage. PATMOS, 2006.
|
 |
12
|
Siva Narendra , Vivek De , Shekhar Borkar , Dimitri Antoniadis , Anantha Chandrakasan, Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
[doi> 10.1145/566408.566415]
|
 |
13
|
Zhanping Chen , Mark Johnson , Liqiong Wei , Kaushik Roy, Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks, Proceedings of the 1998 international symposium on Low power electronics and design, p.239-244, August 10-12, 1998, Monterey, California, United States
[doi> 10.1145/280756.280917]
|
 |
14
|
|
 |
15
|
|
 |
16
|
|
| |
17
|
Y Zhang, D Parikh, M Stan, K Sankaranarayanan, K Skadron: HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects. Tech Report CS-2003-05, Univ. of Virginia Dept. of Computer Science, 2003.
|
 |
18
|
|
| |
19
|
K Banerjee, S-C Lin, A Keshavarzi, S Narendra, V De: A Self-Consistent Junction Temperature Estimation Methodology for Nanometer Scale ICs with Implications for Performance and Thermal Management. IEEE, 2003.
|
 |
20
|
Haihua Su , Frank Liu , Anirudh Devgan , Emrah Acar , Sani Nassif, Full chip leakage estimation considering power supply and temperature variations, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
[doi> 10.1145/871506.871529]
|
 |
21
|
Shekhar Borkar , Tanay Karnik , Siva Narendra , Jim Tschanz , Ali Keshavarzi , Vivek De, Parameter variations and impact on circuits and microarchitecture, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
[doi> 10.1145/775832.775920]
|
| |
22
|
|
|