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Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 2006 international symposium on Low power electronics and design table of contents
Tegernsee, Bavaria, Germany
SESSION: Leakage control and dynamic power optimization table of contents
Pages: 220 - 225  
Year of Publication: 2006
ISBN:1-59593-462-6
Authors
Domenik Helms  OFFIS Research Institute, Oldenburg, Germany
Günter Ehmen  OFFIS Research Institute, Oldenburg, Germany
Wolfgang Nebel  University of Oldenburg, Oldenburg, Germany
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 1,   Downloads (12 Months): 44,   Citation Count: 2
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ABSTRACT

In this work we present a SPICE-based RTL subthreshold-leakage model analyzing components built in 70nm technology [1]. We present a separation approach regarding inter- and intra-die threshold variations, temperature, supply-voltage, and state dependence. The body-effect and differences between NMOS and PMOS introduce a leakage state dependence of one order of magnitude[2, 3]. We show that the leakage of RT-components still shows state dependencies between 20% and $80%. A leakage model not regarding the state can never be more accurate than this. The proposed state aware model has an average error of 6.7% for the RT-components analyzed.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Berkeley Predictive Technology Model: www-device.eecs.berkeley.edu/~ptm/
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K Roy, S Mukhopadhyay, H Mahmoodi-Meimand: Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits. Proc. of the IEEE Vol.91 No.2, 2003.
 
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C Hu: BSIM Model for Circuit Design Using Advanced Technologies. 2001 Symposium on VLSI Circuit Digest of Technical Papers, 2001.
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D Helms, E Schmidt, W Nebel: Leakage in CMOS circuits - An Introduction. PATMOS, 2004.
 
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D Lee D Blaauw, D Sylvester: Static Leakage Reduction Through Simultaneous V_T/T_ox and State Assignment. IEEE Tran on CAD of ICs and Systems Vol24 No7, 2004
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D Helms, M Hoyer, W Nebel: Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage. PATMOS, 2006.
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Y Zhang, D Parikh, M Stan, K Sankaranarayanan, K Skadron: HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects. Tech Report CS-2003-05, Univ. of Virginia Dept. of Computer Science, 2003.
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K Banerjee, S-C Lin, A Keshavarzi, S Narendra, V De: A Self-Consistent Junction Temperature Estimation Methodology for Nanometer Scale ICs with Implications for Performance and Thermal Management. IEEE, 2003.
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Collaborative Colleagues:
Domenik Helms: colleagues
Günter Ehmen: colleagues
Wolfgang Nebel: colleagues