Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designs

ABSTRACT

We present our approach for a new macromodule power model library which can be used in high-level dynamic power estimation for FPGA technologies. The approach adapts a previously published high-level estimation flow for ASIC technologies. Due to the different architectures (ASIC vs. FPGA) the presented approach builds on an iterative optimization step during the model generation phase.

REFERENCES

• 1: Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill Higher Education, 1994
• 2: Gerd Jochens , Lars Kruse , Eike Schmidt , Wolfgang Nebel, A new parameterizable power macro-model for datapath components, Proceedings of the conference on Design, automation and test in Europe, p.8-es, January 1999, Munich, Germany [doi>10.1145/307418.307434]
• 3: Xilinx, Virtex-4 Family Overview http://direct.xilinx.com/bvdocs/publications/ds112.pdf
• 4: A. Monostori, H. H. Frühauf, G. Kokai, Quick Estimation of Resources of FPGAs and ASICs Using Neural Networks in Proceedings of IWA05, 2005.
• 5: S. Bilavarn, G. Gogniat, J. L. Philippe, L. Bossuet, Fast prototyping of reconfigurable architectures from a C program in Proceedings of ISCAS, vol. 5, 2003.
• 6: J. H. Anderson, F. N. Najm, Power-Aware Technology Mapping for LUT-Based FPGAs in Proceedings of ICFPT02, 2002.
• 7: S. Bilavarn, G. Gogniat, J. L. Philippe, FPGA Area Time Power Estimation for DSP Applications in Proceedings of ICSPAT00, 2000.
• 8: Li Shang , Alireza S. Kaviani , Kusuma Bathala, Dynamic power consumption in Virtex™-II FPGA family, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA [doi>10.1145/503048.503072]
• 9: Kara K. W. Poon , Steven J. E. Wilton , Andy Yan, A detailed power model for field-programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.279-302, April 2005 [doi>10.1145/1059876.1059881]
• 10: Varghese George , Jan M. Rabaey, Low-energy FPGAs: architecture and design, Kluwer Academic Publishers, Norwell, MA, 2001
• 11: Jason H. Anderson , Farid N. Najm, Interconnect capacitance estimation for FPGAs, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.713-718, January 27-30, 2004, Yokohama, Japan
• 12: C. Bingham, G. Oehlert An Introduction to MacAnova University of Minnesota, School of Statistics, Technical Report Number 60, 1995

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Measurement, Reliability

Keywords:
FPGA power estimation, RT-level power modeling, high-level power estimation