ACM Home Page
Please provide us with feedback. Feedback
Utilizing reverse short channel effect for optimal subthreshold circuit design
Full text PdfPdf (1.93 MB)
Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 2006 international symposium on Low power electronics and design table of contents
Tegernsee, Bavaria, Germany
POSTER SESSION: Low power circuits and microarchitectures table of contents
Pages: 127 - 130  
Year of Publication: 2006
ISBN:1-59593-462-6
Authors
Tae-Hyoung Kim  University of Minnesota, MN
Hanyong Eom  University of Minnesota, MN
John Keane  University of Minnesota, MN
Chris Kim  University of Minnesota, MN
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 18,   Downloads (12 Months): 46,   Citation Count: 4
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1165573.1165603
What is a DOI?

ABSTRACT

The impact of the Reverse Short Channel Effect (RSCE) on device current is stronger in the subthreshold region due to the reduced Drain-Induced-Barrier-Lowering (DIBL) and the exponential dependency of current on threshold voltage. This paper describes a device size optimization method for subthreshold circuits utilizing RSCE to achieve high drive current, low device capacitance, less sensitivity to random dopant fluctuations, and better subthreshold swing. Simulation results using ISCAS benchmark circuits show that the critical path delay and power consumption can be improved by up to 10.4% and 34.4%, respectively.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
A. Bryant, et al., "Low-power CMOS at Vdd=4kT/q", in Proc. Device Research Conference, pp. 22--23, 2001.
3
 
4
E. Vittoz, et al., "CMOS analog integrated circuits based on weak inversion operations", IEEE J. of Solid-State Circuits, Volume 12, pp. 224--231, June 1977.
 
5
A. Wang, et al., "A 180-mV subthreshold FFT processor using a minimum energy design methodology", IEEE J. of Solid-State Circuits, Volume 40, pp. 310--319, Jan. 2005.
 
6
B.H. Calhoun, et al., "A 256k Sub-threshold SRAM using 65nm CMOS," in Proc. ISSCC, pp. 628--629, Feb. 2006.
 
7
B.H. Calhoun, et al., "Ultra-dynamic voltage scaling using sub-threshold operation and local voltage dithering in 90nm CMOS", in Proc. ISSCC, pp. 300--301, Feb. 2005.
 
8
C.H. Kim, et al., "Ultra-low-power DLMS adaptive filter for hearing aid applications", IEEE Trans. VLSI Systems, Volume 11, pp. 1058--1067, Dec. 2003.
 
9
J.J. Kim, et al., "Double gate-MOSFET subthreshold circuit for ultra-low power applications", IEEE Trans. Electron Devices, Volume 51, pp. 1468--1474, Sept. 2004.
 
10
R. R. Troutman, "VLSI Limitations from drain-induced barrier lowering," IEEE Trans. Electron Devices", Volume 26, pp. 461--469, Apr. 1979.
 
11
C.Y. Lu, et al., "Reverse short-channel effects on threshold voltage in submicrometer salicide devices", IEEE Electron Device Letters, Volume 10, pp. 446--448, Oct. 1989
 
12
C. Subramanian, et al., "Reverse short channel effect and channel length dependence of boron penetration in PMOSFETs", in Proc. IEDM, pp. 423--426, Dec. 1995.
 
13
Y. Taur, et al., "25nm CMOS Design Considerations", in Proc. IEDM, pp. 789--792, Dec. 1998.


Collaborative Colleagues:
Tae-Hyoung Kim: colleagues
Hanyong Eom: colleagues
John Keane: colleagues
Chris Kim: colleagues