Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture

ABSTRACT

In recent years, Globally Asynchronous Locally Synchronous (GALS) designs and dynamic voltage scaling (DVS) have emerged as some of the most popular approaches to address the ever increasing microprocessor energy consumption. In this work, we propose two on-line algorithms for adjusting dynamically, and independently, the voltage and frequency of the front-end and back-end domains of a novel two-domain microprocessor. We evaluate our mechanisms for both internal and external voltage regulators, and we present optimal dynamic voltage scaling results for the proposed microarchitecture. Our schemes achieve average improvement of 12% of the energy-delay² metric, when using internal voltage regulators.

REFERENCES

• 1: David M. Brooks , Pradip Bose , Stanley E. Schuster , Hans Jacobson , Prabhakar N. Kudva , Alper Buyuktosunoglu , John-David Wellman , Victor Zyuban , Manish Gupta , Peter W. Cook, Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors, IEEE Micro, v.20 n.6, p.26-44, November 2000 [doi>10.1109/40.888701]
• 2: David Brooks , Vivek Tiwari , Margaret Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, p.83-94, June 2000, Vancouver, British Columbia, Canada
• 3: Pedro Chaparro , Grigorios Magklis , Jose Gonzalez , Antonio Gonzalez, Distributing the Frontend for Temperature Reduction, Proceedings of the 11th International Symposium on High-Performance Computer Architecture, p.61-70, February 12-16, 2005 [doi>10.1109/HPCA.2005.12]
• 4: Daniel Marcos Chapiro, Globally-asynchronous locally-synchronous systems (performance, reliability, digital), 1985
• 5: Tiberiu Chelcea , Steven M. Nowick, Robust interfaces for mixed-timing systems with application to latency-insensitive protocols, Proceedings of the 38th conference on Design automation, p.21-26, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.378256]
• 6: T. Fischer et al. A 90-nm Variable Frequency Clock System for a Power-Managed Itanium Architecture Processor. IEEE Journal of Solid State Circuits, 41(1), Jan. 2006.
• 7: José González , Antonio González, Dynamic Cluster Resizing, Proceedings of the 21st International Conference on Computer Design, p.375, October 13-15, 2003
• 8: José González , Fernando Latorre , Antonio González, Cache organizations for clustered microarchitectures, Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture, p.46-55, June 20-20, 2004, Munich, Germany [doi>10.1145/1054943.1054950]
• 9: P. Hazucha et al. Area-Efficient Linear Regulator with Ultra-Fast Load Regulation. IEEE Journal of Solid-State Circuits, 40(4), April 2005.
• 10: A. Hemani , T. Meincke , S. Kumar , A. Postula , T. Olsson , P. Nilsson , J. Oberg , P. Ellervee , D. Lundqvist, Lowering power consumption in clock by using globally asynchronous locally synchronous design style, Proceedings of the 36th ACM/IEEE conference on Design automation, p.873-878, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310091]
• 11: Anoop Iyer , Diana Marculescu, Power and performance evaluation of globally asynchronous locally synchronous processors, Proceedings of the 29th annual international symposium on Computer architecture, p.158, May 25-29, 2002, Anchorage, Alaska
• 12: Grigorios Magklis , Jose Gonzalez , Antonio Gonzalez, Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2, Proceedings of the IEEE International Conference on Computer Design (ICCD'04), p.250-255, October 11-13, 2004
• 13: T. Olsson et al. A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs. In International Symposium on Circuits and Systems, May 2000.
• 14: Joan-Manuel Parcerisa , Julio Sahuquillo , Antonio González , José Duato, Efficient Interconnects for Clustered Microarchitectures, Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques, p.291, September 22-25, 2002
• 15: Greg Semeraro , David H. Albonesi , Steven G. Dropsho , Grigorios Magklis , Sandhya Dwarkadas , Michael L. Scott, Dynamic frequency and voltage control for a multiple clock domain microarchitecture, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
• 16: G. Semeraro et al. Hiding Synchronization Delays in a GALS Processor Microarchitecture. In International Symposium on Asynchronous Circuits and Systems, April 2004.
• 17: Greg Semeraro , Grigorios Magklis , Rajeev Balasubramonian , David H. Albonesi , Sandhya Dwarkadas , Michael L. Scott, Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling, Proceedings of the 8th International Symposium on High-Performance Computer Architecture, p.29, February 02-06, 2002
• 18: P. Shivakumar and N. P. Jouppi. CACTI 3.0: An Integrated Cache Timing, Power, and Area Model. WRL Research Report 2001/2, Aug. 2001.
• 19: Qiang Wu , Philo Juang , Margaret Martonosi , Douglas W. Clark, Formal online methods for voltage/frequency control in multiple clock domain microprocessors, Proceedings of the 11th international conference on Architectural support for programming languages and operating systems, October 07-13, 2004, Boston, MA, USA
• 20: Qiang Wu , Philo Juang , Margaret Martonosi , Douglas W. Clark, Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors, Proceedings of the 11th International Symposium on High-Performance Computer Architecture, p.178-189, February 12-16, 2005 [doi>10.1109/HPCA.2005.43]
• 21: Y. Zhang et al. HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects. Technical Report CS-2003-05, Dept. of Computer Science, University of Virginia, Mar. 2003.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.0 General

General Terms:
Algorithms, Design

Keywords:
DVS, GALS, MCD, energy efficiency, microarchitecture