Selective writeback: exploiting transient values for energy-efficiency and performance

ABSTRACT

Today's superscalar microprocessors use large, heavily-ported physical register files (RFs) to increase the instruction throughput. The high complexity and power dissipation of such RFs mainly stem from the need to maintain each and every result for a large number of cycles after the result generation. We observed that a significant fraction (about 45%) of the result values are delivered to their consumers via the bypass network (consumed "on-the-fly") and are never read out from the destination registers. In this paper, we first formulate conditions for identifying such transient values and describe their micro-architectural implementation; then we propose a technique to avoid the writeback of such transient values into the RF. With 64-entry integer and floating point register files, our technique achieves an 11% performance improvement and 29% reduction in the RF energy consumption compared to the baseline machine with the same number of registers. Furthermore, for the same performance target, the Selective Writeback scheme results in a 38% reduction in the energy consumption of the RF compared to the baseline machine.

REFERENCES

• 1: Aneesh Aggarwal , Manoj Franklin, Energy Efficient Asymmetrically Ported Register Files, Proceedings of the 21st International Conference on Computer Design, p.2, October 13-15, 2003
• 2: A. Azevedo , I. Issenin , R. Cornea , R. Gupta , N. Dutt , A. Veidenbaum , A. Nicolau, Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints, Proceedings of the conference on Design, automation and test in Europe, p.168, March 04-08, 2002
• 3: Saisanthosh Balakrishnan , Gurindar S. Sohi, Exploiting Value Locality in Physical Register Files, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.265, December 03-05, 2003
• 4: Rajeev Balasubramonian , Sandhya Dwarkadas , David H. Albonesi, Reducing the complexity of the register file in dynamic superscalar processors, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
• 5: Eric Borch , Srilatha Manne , Joel Emer , Eric Tune, Loose Loops Sink Chips, Proceedings of the 8th International Symposium on High-Performance Computer Architecture, p.299, February 02-06, 2002
• 6: Burger, D. and Austin, T. M., "The SimpleScalar tool set: Version 2.0", Tech. Report, Dept. of CS, Univ. of Wisconsin-Madison, June 1997.
• 7: George Z. Chrysos , Joel S. Emer, Memory dependence prediction using store sets, Proceedings of the 25th annual international symposium on Computer architecture, p.142-153, June 27-July 02, 1998, Barcelona, Spain
• 8: José-Lorenzo Cruz , Antonio González , Mateo Valero , Nigel P. Topham, Multiple-banked register file architectures, Proceedings of the 27th annual international symposium on Computer architecture, p.316-325, June 2000, Vancouver, British Columbia, Canada
• 9: Oguz Ergin , Deniz Balkan , Dmitry Ponomarev , Kanad Ghose, Increasing Processor Performance Through Early Register Release, Proceedings of the IEEE International Conference on Computer Design (ICCD'04), p.480-487, October 11-13, 2004
• 10: Oguz Ergin , Deniz Balkan , Kanad Ghose , Dmitry Ponomarev, Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.304-315, December 04-08, 2004, Portland, Oregon [doi>10.1109/MICRO.2004.29]
• 11: A. González , J. González , M. Valero, Virtual-Physical Registers, Proceedings of the 4th International Symposium on High-Performance Computer Architecture, p.175, January 31-February 04, 1998
• 12: Gonzalez Gonzalez , Adrian Cristal , Daniel Ortega , Alexander Veidenbaum , Mateo Valero, A Content Aware Integer Register File Organization, Proceedings of the 31st annual international symposium on Computer architecture, p.314, June 19-23, 2004, München, Germany
• 13: Timothy M. Jones , Michael F. P. O'Boyle , Jaume Abella , Antonio Gonzalez , Oğuz Ergin, Compiler Directed Early Register Release, Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques, p.110-122, September 17-21, 2005 [doi>10.1109/PACT.2005.14]
• 14: Stephen Jourdan , Ronny Ronen , Michael Bekerman , Bishara Shomar , Adi Yoaz, A novel renaming scheme to exploit value temporal locality through physical register reuse and unification, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.216-225, November 1998, Dallas, Texas, United States
• 15: Nam Sung Kim , Trevor Mudge, Reducing register ports using delayed write-back queues and operand pre-fetch, Proceedings of the 17th annual international conference on Supercomputing, June 23-26, 2003, San Francisco, CA, USA [doi>10.1145/782814.782839]
• 16: Masaaki Kondo , Hiroshi Nakamura, A Small, Fast and Low-Power Register File by Bit-Partitioning, Proceedings of the 11th International Symposium on High-Performance Computer Architecture, p.40-49, February 12-16, 2005 [doi>10.1109/HPCA.2005.3]
• 17: Mikko H. Lipasti , Brian R. Mestan , Erika Gunadi, Physical Register Inlining, Proceedings of the 31st annual international symposium on Computer architecture, p.325, June 19-23, 2004, München, Germany
• 18: Luis A. Lozano , Guang R. Gao, Exploiting short-lived variables in superscalar processors, Proceedings of the 28th annual international symposium on Microarchitecture, p.292-302, November 29-December 01, 1995, Ann Arbor, Michigan, United States
• 19: Milo M. Martin , Amir Roth , Charles N. Fischer, Exploiting dead value information, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.125-135, December 01-03, 1997, Research Triangle Park, North Carolina, United States
• 20: José F. Martínez , Jose Renau , Michael C. Huang , Milos Prvulovic , Josep Torrellas, Cherry: checkpointed early resource recycling in out-of-order microprocessors, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
• 21: Teresa Monreal , Víctor Viñals , Antonio González , Mateo Valero, Hardware Schemes for Early Register Release, Proceedings of the 2002 International Conference on Parallel Processing (ICPP'02), p.5, August 18-21, 2002
• 22: Il Park , Michael D. Powell , T. N. Vijaykumar, Reducing register ports for higher speed and lower energy, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
• 23: Dmitry Ponomarev , Gurhan Kucuk , Oguz Ergin , Kanad Ghose, Reducing Datapath Energy through the Isolation of Short-Lived Operands, Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques, p.258, September 27-October 01, 2003
• 24: Jessica H. Tseng , Krste Asanović, Banked multiported register files for high-frequency superscalar microprocessors, Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003, San Diego, California

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.1 Single Data Stream Architectures

General Terms:
Design, Performance

Keywords:
energy-efficiency, register files